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公开(公告)号：US10908832B2
公开(公告)日：2021-02-02
申请号：US15799508
申请日：2017-10-31
Applicant: Micron Technology, Inc.
Inventor： Kulachet Tanpairoj , Sebastien Andre Jean , Jianmin Huang
Abstract: Disclosed in some examples are methods, systems, machine-readable mediums, and NAND devices which create logical partitions when requested to create a physical partition. The controller on the NAND mimics the creation of the physical partition to the host device that requested the physical partition. Thus, the host device sees the logical partition as a physical partition. Despite this, the NAND does not incur the memory storage expense of creating a separate partition, and additionally the NAND can borrow cells for overprovisioning from another partition. In these examples, a host device operating system believes that a physical partition has been created, but the NAND manages the memory as a contiguous pool of resources. Thus, a logical partition is created at the NAND memory controller level—as opposed to at the operating system level.
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公开(公告)号：US10559369B2
公开(公告)日：2020-02-11
申请号：US16405192
申请日：2019-05-07
Applicant: Micron Technology, Inc.
Inventor： Sebastien Andre Jean , Harish Reddy Singidi
Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.
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公开(公告)号：US20200043559A1
公开(公告)日：2020-02-06
申请号：US16542963
申请日：2019-08-16
Applicant: Micron Technology, Inc.
Inventor： Greg A. Blodgett , Sebastien Andre Jean
IPC: G11C16/34 , G06F12/14 , G11C7/04 , G06F1/3206 , G11C16/04
Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.
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公开(公告)号：US20200035314A1
公开(公告)日：2020-01-30
申请号：US16589956
申请日：2019-10-01
Applicant: Micron Technology, Inc.
Inventor： Sebastien Andre Jean
IPC: G11C16/34 , G01R31/3193 , G11C29/52
Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.
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公开(公告)号：US10545685B2
公开(公告)日：2020-01-28
申请号：US15690869
申请日：2017-08-30
Applicant: Micron Technology, Inc.
Inventor： Kulachet Tanpairoj , Sebastien Andre Jean , Kishore Kumar Muchherla , Ashutosh Malshe , Jianmin Huang
IPC: G06F12/00 , G06F3/06 , G06F12/0811
Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.
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Patent Agency Ranking
公开(公告)号：US10418115B2
公开(公告)日：2019-09-17
申请号：US16023926
申请日：2018-06-29
Applicant: Micron Technology, Inc.
Inventor： Greg A. Blodgett , Sebastien Andre Jean
Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.
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公开(公告)号：US20190265975A1
公开(公告)日：2019-08-29
申请号：US16409062
申请日：2019-05-10
Applicant: Micron Technology, Inc.
Inventor： Sebastien Andre Jean
IPC: G06F9/30
Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A memory controller can receive instructions from a host device, determine an initial priority for each instruction using QoS parameters, and allocate the received instructions to the number of memory dies using the initial priority. The memory controller can maintain separate schedules for each of the number or memory dies, update the initial priority for each instruction with the separate schedules, and maintain each of the separate schedules using the updated priority for each instruction in the respective separate schedule.
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公开(公告)号：US20190129641A1
公开(公告)日：2019-05-02
申请号：US15799508
申请日：2017-10-31
Applicant: Micron Technology, Inc.
Inventor： Kulachet Tanpairoj , Sebastien Andre Jean , Jianmin Huang
Abstract: Disclosed in some examples are methods, systems, machine-readable mediums, and NAND devices which create logical partitions when requested to create a physical partition. The controller on the NAND mimics the creation of the physical partition to the host device that requested the physical partition. Thus, the host device sees the logical partition as a physical partition. Despite this, the NAND does not incur the memory storage expense of creating a separate partition, and additionally the NAND can borrow cells for overprovisioning from another partition. In these examples, a host device operating system believes that a physical partition has been created, but the NAND manages the memory as a contiguous pool of resources. Thus, a logical partition is created at the NAND memory controller level—as opposed to at the operating system level.
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公开(公告)号：US20190065393A1
公开(公告)日：2019-02-28
申请号：US15692622
申请日：2017-08-31
Applicant: Micron Technology, Inc.
Inventor： Sebastien Andre Jean
IPC: G06F12/1009
CPC classification number: G06F12/1009 , G06F12/0246 , G06F2212/1024 , G06F2212/1044 , G06F2212/7201
Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.
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公开(公告)号：US20190065388A1
公开(公告)日：2019-02-28
申请号：US15691147
申请日：2017-08-30
Applicant: Micron Technology, Inc.
Inventor： Carla L. Christensen , Jianmin Huang , Sebastien Andre Jean , Kulachet Tanpairoj
IPC: G06F12/0893
Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.
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