公开(公告)号：US11599366B2

公开(公告)日：2023-03-07

申请号：US17465505

申请日：2021-09-02

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett

IPC: G06F9/4401 ,  G06F13/16 ,  G06F1/3296 ,  G06F3/06

Abstract: Systems and methods are disclosed, including selectively providing one of a first reset or a second reset to transition to a storage system from a low power mode to an operational power mode in response to a hardware reset signal and a value of a control bit on the storage system.

公开(公告)号：US11409651B2

公开(公告)日：2022-08-09

申请号：US17051995

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/14

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

公开(公告)号：US11309040B2

公开(公告)日：2022-04-19

申请号：US17147222

申请日：2021-01-12

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F1/32 ,  G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F12/14 ,  G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F12/02 ,  G06F21/79 ,  H04L9/08 ,  G06F1/3234 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

公开(公告)号：US10109357B2

公开(公告)日：2018-10-23

申请号：US14867985

申请日：2015-09-28

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett

IPC: G06F11/00 ,  G11C16/34 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G11C11/56 ,  G11C16/26

Abstract: Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

公开(公告)号：US20220404988A1

公开(公告)日：2022-12-22

申请号：US17895737

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F3/06 ,  G06F21/60 ,  G06F21/79

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

公开(公告)号：US20210334016A1

公开(公告)日：2021-10-28

申请号：US16485374

申请日：2019-04-11

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F3/06 ,  G06F21/60 ,  G06F21/79

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

公开(公告)号：US11113073B2

公开(公告)日：2021-09-07

申请号：US16425127

申请日：2019-05-29

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett

IPC: G06F9/4401 ,  G06F13/16 ,  G06F1/3296 ,  G06F3/06

Abstract: Systems and methods are disclosed, including selectively providing one of a first reset or a second reset to transition to a storage system from a low power mode to an operational power mode in response to a hardware reset signal and a value of a control bit on the storage system.

公开(公告)号：US11442634B2

公开(公告)日：2022-09-13

申请号：US16485374

申请日：2019-04-11

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F21/60 ,  G06F21/79

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

公开(公告)号：US10916316B2

公开(公告)日：2021-02-09

申请号：US17016182

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F12/14 ,  G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F12/02 ,  G06F21/79 ,  H04L9/08 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

公开(公告)号：US10790032B2

公开(公告)日：2020-09-29

申请号：US16542963

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F12/14 ,  G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F3/06 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.