公开(公告)号：US11803391B2

公开(公告)日：2023-10-31

申请号：US17075399

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F9/38 ,  G06F9/48 ,  G06F15/78 ,  H01L25/065

CPC classification number: G06F9/3851 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/48 ,  G06F9/4887 ,  H01L25/0655 ,  G06F15/7825

Abstract: Devices and techniques for threads in a programmable atomic unit to self-schedule are described herein. When it is determined that an instruction will not complete within a threshold prior to insertion into a pipeline of the processor, a thread identifier (ID) can be passed with the instruction. Here, the thread ID corresponds to a thread of the instruction. When a response to completion of the instruction is received that includes the thread ID, the thread is rescheduled using the thread ID in the response.

公开(公告)号：US20230251894A1

公开(公告)日：2023-08-10

申请号：US17074811

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F9/46 ,  G06F9/30 ,  G06F15/78

CPC classification number: G06F9/467 ,  G06F9/3004 ,  G06F15/7825

Abstract: Chiplet systems may include a memory controller that has programmable atomic units that execute programmable atomic transactions. These instructions are stored in one or more memory partitions of memory in the programmable atomic unit. Since the programmable atomic unit executes programmable atomic transactions that are customized for various processes, and since the programmable atomic unit is a physical resource shared by multiple processes, the processes need a way of both loading the programmable atomic unit memory with instructions and a method of calling those instructions. Disclosed are methods, systems, and devices for registering, calling, and virtualizing programmable atomic transactions.

公开(公告)号：US11658922B2

公开(公告)日：2023-05-23

申请号：US17007224

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer ,  David Patrick

IPC: H04L49/109 ,  H04L47/34 ,  H04L69/22 ,  G06F15/78

CPC classification number: H04L49/109 ,  H04L47/34 ,  H04L69/22 ,  G06F15/7825

Abstract: A system may include multiple electronic devices and multiple hardware transceivers. The multiple electronic devices may include multiple chiplets and may be coupled to each other via an interface network. The multiple hardware transceivers may each be included in or coupled to a respective electronic device of the multiple electronic devices. The multiple hardware transceivers may each be configured to receive data packets from a source device. The data packets each include a protocol field specifying ordering information for delivery to a destination device and a path field specifying path information for routing the delivery to the destination device. The source device and the destination device may each include a chiplet. The multiple hardware transceivers may each be further configured to transmit the received data packets to the destination device using at least the ordering information of each received data packet.

公开(公告)号：US11586439B2

公开(公告)日：2023-02-21

申请号：US17074834

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F9/30 ,  G06F12/0815 ,  G06F12/0875

Abstract: Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

公开(公告)号：US20230004524A1

公开(公告)日：2023-01-05

申请号：US17901480

申请日：2022-09-01

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F15/82 ,  G06F9/4401

Abstract: Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

公开(公告)号：US11520718B2

公开(公告)日：2022-12-06

申请号：US17075365

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/16 ,  G06F12/0862

Abstract: Devices and techniques for managing hazards in a memory controller are described herein. The memory controller can receive a memory request that includes a base memory address. An index can be computed from the base memory address and a lookup, using the index, can be performed to find a lock. When the lock is found, the memory controller can store the memory request in a buffer that corresponds to the lock. In response to a signal to clear the lock, the memory controller removes the memory request from the buffer and performs the memory request.

公开(公告)号：US20220382557A1

公开(公告)日：2022-12-01

申请号：US17880230

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Tony Brewer ,  Chris Baronne

IPC: G06F9/4401 ,  G06F12/14

Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.

公开(公告)号：US20220360649A1

公开(公告)日：2022-11-10

申请号：US17865141

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： David Patrick ,  Tony Brewer

IPC: H04L69/22 ,  H04L47/2441 ,  H04L69/16

Abstract: Implementations of the present disclosure are directed to systems and methods for processing headers that support multiple protocols. A header of a packet includes a bridge type (BTYPE) field that indicates the protocol of the packet. A command field of the packet is interpreted differently based on the value of the BTYPE field. Among the benefits of implementations of the present disclosure is that a single network may be used to carry packets of different protocols without the overhead of encapsulation.

公开(公告)号：US11488643B2

公开(公告)日：2022-11-01

申请号：US17007876

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Tony Brewer

IPC: G11C7/10 ,  G06F9/30 ,  G06F13/16 ,  H01L23/538

Abstract: A system comprises an interposer including multiple conductive interconnects; multiple chiplets arranged on the interposer and interconnected by the interposer; each chiplet including a die-to-die physical layer interface including one or more pads to engage the interconnect of the interposer; and wherein at least one chiplet includes multiple input-output channels organized into at least one column and arranged in an order at a periphery of the chiplet forming a die-to-die physical layer interface to engage the interconnects of the interposer, wherein the order of the channels of the column is programmable.

公开(公告)号：US20220300447A1

公开(公告)日：2022-09-22

申请号：US17831856

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Tony Brewer

IPC: G06F13/40 ,  G06F13/42

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.