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公开(公告)号：US20240332257A1
公开(公告)日：2024-10-03
申请号：US18734765
申请日：2024-06-05
发明人： Michael G. Placke , Tony Brewer
IPC分类号： H01L25/065 , H01L23/00
CPC分类号： H01L25/0655 , H01L24/16
摘要： A chiplet-based system comprises a substrate including conductive interconnect and multiple chiplets arranged on the interposer and interconnected using the conductive interconnect of the substrate. A chiplet includes multiple columns of multiple input-output (I/O) channels and the I/O channels are connected to a block of I/O pads and each side of the chiplet includes multiple blocks of the I/O pads. The multiple blocks of I/O pads on the side of the chiplet are arranged symmetrically relative to a centerline of the chiplet and each block of I/O pads on the side of the chiplet is at a common distance from any adjacent block of I/O pads on the side.
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公开(公告)号：US11954055B2
公开(公告)日：2024-04-09
申请号：US17744085
申请日：2022-05-13
发明人： David Patrick , Tony Brewer
CPC分类号： G06F13/385 , G06F13/4031 , G06F13/4282 , H04L45/74
摘要： Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.
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公开(公告)号：US11734173B2
公开(公告)日：2023-08-22
申请号：US17854770
申请日：2022-06-30
发明人： Tony Brewer , Dean E. Walker , Chris Baronne
IPC分类号： G06F12/00 , G06F12/06 , G06F12/02 , G06F12/0844
CPC分类号： G06F12/0607 , G06F12/0223 , G06F12/0844 , G06F2212/1012
摘要： Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.
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公开(公告)号：US11698791B2
公开(公告)日：2023-07-11
申请号：US17880230
申请日：2022-08-03
发明人： Dean E. Walker , Tony Brewer , Chris Baronne
IPC分类号： G06F9/4401 , G06F12/14
CPC分类号： G06F9/4403 , G06F12/1458 , G06F12/14 , G06F2212/1052 , Y02D10/00
摘要： Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.
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公开(公告)号：US20230215500A1
公开(公告)日：2023-07-06
申请号：US18117900
申请日：2023-03-06
发明人： Tony Brewer
IPC分类号： G11C16/10 , G11C16/34 , G11C16/08 , G11C16/26 , G06F13/16 , G06F12/0862 , G06F12/0875 , G06F9/52 , G06F12/0815
CPC分类号： G11C16/102 , G11C16/3459 , G11C16/08 , G11C16/26 , G06F13/1605 , G06F13/1668 , G06F12/0862 , G06F12/0875 , G06F9/526 , G06F12/0815 , G06F2212/1024
摘要： Devices and techniques for programmable atomic operator resource locking are described herein. A request for a programmable atomic operator (PAO) can be received at a memory controller that includes a programmable atomic unit (PAU). Here, the request includes an identifier for the PAO and a memory address. The memory addressed is processed to identify a lock value. A verification can be performed to determine that the lock value indicates that there is no lock corresponding to the memory address. Then, the lock value is set to indicate that there is now a lock corresponding to the memory address and the PAO is invoked based on the identifier for the PAO. In response to completion of the PAO, the lock value is set to indicate that there is no longer a lock corresponding to the memory address.
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公开(公告)号：US20220414004A1
公开(公告)日：2022-12-29
申请号：US17854770
申请日：2022-06-30
发明人： Tony Brewer , Dean E. Walker , Chris Baronne
摘要： Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.
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公开(公告)号：US11526361B2
公开(公告)日：2022-12-13
申请号：US17074722
申请日：2020-10-20
发明人： Tony Brewer
摘要： Devices and techniques for variable pipeline length in a barrel-multithreaded processor are described herein. A completion time for an instruction can be determined prior to insertion into a pipeline of a processor. A conflict between the instruction and a different instruction based on the completion time can be detected. Here, the different instruction is already in the pipeline and the conflict detected when the completion time equals the previously determined completion time for the different instruction. A difference between the completion time and an unconflicted completion time can then be calculated and completion of the instruction delayed by the difference.
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公开(公告)号：US11436187B2
公开(公告)日：2022-09-06
申请号：US17074779
申请日：2020-10-20
发明人： Tony Brewer
IPC分类号： G06F15/82 , G06F9/4401
摘要： Methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).
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公开(公告)号：US20220191149A1
公开(公告)日：2022-06-16
申请号：US17685073
申请日：2022-03-02
发明人： Tony Brewer
摘要： Implementations of the present disclosure are directed to systems and methods for reducing the size of packet headers without reducing the range of packet lengths supported. A packet header includes a fixed-width length field. Using a linear encoding, the maximum packet size is a linear function of the fixed-width length field. Thus, to expand the range of sizes available, either the granularity of the field must be decreased (e.g., by changing the measure of the field from flits to double-flits) or the size of the field must be increased (e.g., by changing the size of the field from 4 bits to 5 bits). However, by using a non-linear encoding, the difference between the minimum and maximum size can be increased without decreasing the granularity within a first range of field values and without increasing the size of the length field.
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公开(公告)号：US11362939B2
公开(公告)日：2022-06-14
申请号：US17007468
申请日：2020-08-31
发明人： Tony Brewer
IPC分类号： H04L45/586 , H04L45/74 , H04L49/00 , H04L45/00 , H04L69/22
摘要： Implementations of the present disclosure are directed to systems and methods for flow control using a multiple flit interface. A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. The amount of buffer space used by the receiver to store the packet is determined by the number of transfer cycles used to receive the packet, not the number of flits comprising the packet. This is enabled by having the buffer be as wide as the bus. The receiver returns credits to the sender based on the number of buffer rows used to store the received packet, not the number of flits comprising the packet.
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