公开(公告)号：US20210066332A1

公开(公告)日：2021-03-04

申请号：US17071980

申请日：2020-10-15

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/285 ,  H01L27/11565

Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

公开(公告)号：US10916564B2

公开(公告)日：2021-02-09

申请号：US16866236

申请日：2020-05-04

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/1157

Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

公开(公告)号：US20210005732A1

公开(公告)日：2021-01-07

申请号：US16458400

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20200312880A1

公开(公告)日：2020-10-01

申请号：US16903201

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  E. Allen McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565

Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.

公开(公告)号：US20200266210A1

公开(公告)日：2020-08-20

申请号：US16866236

申请日：2020-05-04

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11556

Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

公开(公告)号：US20200075620A1

公开(公告)日：2020-03-05

申请号：US16542675

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Tom George ,  Jordan D. Greenlee ,  Scott M. Pook ,  John Mark Meldrim

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

公开(公告)号：US10475810B2

公开(公告)日：2019-11-12

申请号：US16023124

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Sudip Bandyopadhyay ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Anurag Jindal ,  David Ross Economy ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.

公开(公告)号：US20190333924A1

公开(公告)日：2019-10-31

申请号：US16443491

申请日：2019-06-17

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/285

Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

公开(公告)号：US10361214B2

公开(公告)日：2019-07-23

申请号：US16186042

申请日：2018-11-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L21/285 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

公开(公告)号：US10344398B2

公开(公告)日：2019-07-09

申请号：US14989097

申请日：2016-01-06

Applicant: Micron Technology, Inc.

Inventor： John Mark Meldrim ,  Yushi Hu ,  Yongjun Jeff Hu ,  Everett Allen McTeer

IPC: C30B23/02 ,  C30B29/38 ,  H01L27/11556 ,  H01L29/792 ,  H01L27/11582 ,  C30B25/02 ,  H01L21/225 ,  H01L27/11524 ,  H01L27/1157

Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.