公开(公告)号：US20230395149A1

公开(公告)日：2023-12-07

申请号：US17851865

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  David Ross Economy ,  John D. Hopkins ,  Nancy M. Lomeli ,  Jiewei Chen ,  Rita J. Klein ,  Everett A. McTeer ,  Aaron P. Thurber

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20210287960A1

公开(公告)日：2021-09-16

申请号：US17196667

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Pengyuan Zheng

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535

Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.

公开(公告)号：US20240347418A1

公开(公告)日：2024-10-17

申请号：US18640682

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/3736 ,  H01L21/02186 ,  H01L21/0234 ,  H01L21/768 ,  H01L23/535

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US12087358B2

公开(公告)日：2024-09-10

申请号：US17236700

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Stephen W. Russell

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C13/003 ,  H10B63/84 ,  H10N70/021 ,  H10N70/801

Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.

公开(公告)号：US20230209810A1

公开(公告)日：2023-06-29

申请号：US18046088

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  David Ross Economy ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/7682 ,  H01L27/1087 ,  H01L21/76837

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus. A computing system includes the memory device.

公开(公告)号：US20220165793A1

公开(公告)日：2022-05-26

申请号：US17534953

申请日：2021-11-24

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Andrew Leslie Beemer

IPC: H01L27/24 ,  H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L45/00 ,  H01L23/532 ,  H01L23/528

Abstract: Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.

公开(公告)号：US11158561B2

公开(公告)日：2021-10-26

申请号：US16400956

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L23/535 ,  H01L21/768 ,  H01L21/02

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US20200350226A1

公开(公告)日：2020-11-05

申请号：US16400956

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US20230397423A1

公开(公告)日：2023-12-07

申请号：US18307698

申请日：2023-04-26

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  Yongjun J. Hu ,  Pavan Reddy Kumar Aella ,  David Ross Economy ,  Brittany L. Kohoutek ,  Amritesh Rai

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A method of forming a microelectronic device includes forming conductive interconnect structures vertically extending through isolation material to conductive contact structures coupled to pillar structures, forming a metal silicide material on the interconnect structures and the first isolation material, forming a conductive material on the metal silicide material, and forming a dielectric material over the conductive material. The method further includes forming openings vertically extending through the dielectric material, the conductive material, the metal silicide material, and the isolation material and forming additional isolation material to extend over remaining portions of the dielectric material and at least partially fill the openings. Related devices and systems are disclosed.

公开(公告)号：US20230207458A1

公开(公告)日：2023-06-29

申请号：US18046111

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  David Ross Economy ,  Jay S. Brown ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Rita J. Klein

IPC: H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches. The method also includes recessing the first electrically conductive material and replacing removed portions of the first electrically conductive material with a second electrically conductive material.