公开(公告)号：US20160064045A1

公开(公告)日：2016-03-03

申请号：US14826481

申请日：2015-08-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4091 ,  G11C11/4096

Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

Abstract translation: 示例性设备包括耦合到感测电路的存储器单元的阵列。 该装置可以包括控制部件，该控制部件被配置为使得计算等于掩模的数字与存储在存储单元中的逻辑或之间的数据值的数据值 存储在数组中的向量。 控制组件可以使位于与向量的数字对应的阵列的列中的存储单元中存储等于逻辑或的数据值。

公开(公告)号：US11853578B2

公开(公告)日：2023-12-26

申请号：US17512588

申请日：2021-10-27

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/0895 ,  G06F12/0866

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0679 ,  G06F3/068 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0866 ,  G06F12/0895

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.

公开(公告)号：US11782626B2

公开(公告)日：2023-10-10

申请号：US17511142

申请日：2021-10-26

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.

公开(公告)号：US11709613B2

公开(公告)日：2023-07-25

申请号：US17580305

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0685

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US20230161507A1

公开(公告)日：2023-05-25

申请号：US18095878

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0673 ,  G06F3/0604

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US20230053291A1

公开(公告)日：2023-02-16

申请号：US17975164

申请日：2022-10-27

Applicant: Micron Technology. Inc/

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F12/06 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/33 ,  H04W4/029 ,  H04W4/02

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US11507504B2

公开(公告)日：2022-11-22

申请号：US17204522

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F13/00 ,  G06F12/06 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/33 ,  H04W4/029 ,  H04W4/02 ,  G06F9/30 ,  H04B17/24 ,  H04W84/12 ,  H04L101/622 ,  H04L101/69

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US11442648B2

公开(公告)日：2022-09-13

申请号：US16995122

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US20220179590A1

公开(公告)日：2022-06-09

申请号：US17682670

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Dhawal Bavishi ,  Patrick A. La Fratta

IPC: G06F3/06 ,  G06F12/0802

Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.

公开(公告)号：US20220113887A1

公开(公告)日：2022-04-14

申请号：US17511142

申请日：2021-10-26

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.