公开(公告)号：US07007212B2

公开(公告)日：2006-02-28

申请号：US10387132

申请日：2003-03-13

申请人： Yoshihide Komatsu ,  Toru Iwata

发明人： Yoshihide Komatsu ,  Toru Iwata

IPC分类号： G01R31/28

CPC分类号： G01R31/31716

摘要： The present invention provides a transmission device, a reception device, a test circuit and a test method, which enable internal parts of the circuit to operate at high speed, while performing inputting/outputting to/from a tester at low speed. The test circuit comprises a PLL 111 which divides the frequency of a test clock input from the tester to generate a PLL clock CKp1, a FIFO 113 which stores input data input from the tester on the test clock and outputs the data on the PLL clock CKp1, an encoder 114 which distributes bits of the input data, a driver 115 which transmits the output signal from the encoder 114 to the outside, a PLL 121 which divides the frequency of the test clock to generate a PLL clock CKp2, a decoder 124 which arranges the bits of the signal received by a receiver 123.

摘要翻译： 本发明提供了一种在低速地进行/从测试仪输入/输出的同时使得电路的内部部分能够高速运行的发送装置，接收装置，测试电路和测试方法。 测试电路包括一个PLL 111，它分频输入测试时钟的频率，产生一个PLL时钟CKp 1，一个FIFO 113，它将测试时输入的输入数据存储在测试时钟上，并输出PLL时钟上的数据 CKp 1，分配输入数据的位的编码器114，将来自编码器114的输出信号发送到外部的驱动器115，分频测试时钟的频率以产生PLL时钟CKp 2的PLL 121; 解码器124，其布置由接收器123接收的信号的位。

公开(公告)号：US06944003B2

公开(公告)日：2005-09-13

申请号：US10365527

申请日：2003-02-13

申请人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

发明人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

IPC分类号： G01R31/28 ,  H01L21/66 ,  H02H9/04 ,  H02H3/24

CPC分类号： H02H9/046

摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.

摘要翻译： 第一半导体集成电路通过电缆连接到第二半导体集成电路。 在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。 第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。 在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作 强制。 因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。 因此，在低电压条件下可以进行运行评估。

公开(公告)号：US20050024084A1

公开(公告)日：2005-02-03

申请号：US10855351

申请日：2004-05-28

申请人： Takashi Hirata ,  Toru Iwata

发明人： Takashi Hirata ,  Toru Iwata

IPC分类号： G05F1/56 ,  H04L25/02 ,  H03K19/003

CPC分类号： H04L25/0278 ,  G05F1/56 ,  H04L25/028 ,  H04L25/0292

摘要： A terminal resistor built in a signal-sending or signal-receiving semiconductor integrated circuit is composed of a parallel circuit of a polysilicon resistor element having excellent frequency characteristic and a P-type MOS transistor. The resistance value of the polysilicon resistor element is set so as to be an approximate value of the characteristic impedance of a transmission line to be connected. The gate voltage of the P-type MOS transistor is controlled by a gate bias voltage adjustment circuit. The resistance value of the P-type MOS transistor is variably adjusted. Variation in the resistance value of the polysilicon resistor element due to dispersion in its manufacturing process is absorbed by variably adjusting the resistance value of the P-type MOS transistor. The combined resistance value of the polysilicon resistor element and the P-type MOS transistor is adjusted with high precision just to the characteristic impedance of the transmission line. Thus, a signal-sending or signal-receiving semiconductor integrated circuit in which the terminal resistor having excellent frequency and DC characteristics is built can be obtained.

摘要翻译： 内置在信号发送或信号接收半导体集成电路中的端子电阻由具有优异频率特性的多晶硅电阻元件和P型MOS晶体管的并联电路组成。 将多晶硅电阻元件的电阻值设定为要连接的传输线的特性阻抗的近似值。 P型MOS晶体管的栅极电压由栅极偏置电压调节电路控制。 可变地调节P型MOS晶体管的电阻值。 通过可变地调节P型MOS晶体管的电阻值来吸收由于其制造过程中的分散而导致的多晶硅电阻元件的电阻值的变化。 与传输线的特性阻抗相比，多晶硅电阻元件和P型MOS晶体管的组合电阻值被高精度地调整。 因此，可以获得其中构建具有优异的频率和DC特性的端子电阻器的信号发送或信号接收半导体集成电路。

公开(公告)号：US06794912B2

公开(公告)日：2004-09-21

申请号：US10361610

申请日：2003-02-11

申请人： Takashi Hirata ,  Toru Iwata

发明人： Takashi Hirata ,  Toru Iwata

IPC分类号： H03D324

CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/1504 ,  H03L7/07 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/0814

摘要： A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.

摘要翻译： 多相时钟传输电路包括：时钟发生器，用于响应于参考时钟和所产生的时钟之间的相位差，产生与参考时钟同步的时钟和控制信号; 以及用于基于时钟和控制信号产生多相时钟的延迟电路。 时钟发生器产生具有等于参考时钟的频率的整数倍的频率的信号，并将该信号作为时钟输出。 延迟电路具有接收时钟并且包括多个级联连接的延迟元件的电路，每个延迟元件根据与输入信号的控制信号给出延迟。 将从多个延迟元件输出的信号用作构成多相时钟的信号。

公开(公告)号：US06551185B1

公开(公告)日：2003-04-22

申请号：US09647499

申请日：2000-11-07

申请人： Kunihiko Miyake ,  Yoshimasa Kikuchi ,  Toru Iwata ,  Masashi Kamada

发明人： Kunihiko Miyake ,  Yoshimasa Kikuchi ,  Toru Iwata ,  Masashi Kamada

IPC分类号： F24F7007

CPC分类号： F24F7/10 ,  F24F1/0011 ,  F24F13/15 ,  F24F2001/0037 ,  F24F2001/0051 ,  F24F2001/0055 ,  F24F2003/1632 ,  F24F2003/1682

摘要： An air intake and blowing device, comprising a blowing fan (11) such as a turbo fan capable of blowing air in all directions which is installed inside a main casing (2) provided with an air intake port (5) and an air blowing port (9) enclosing the air intake port (5), the air blowing port (9) being provided with a vortex flow creating member which creates a spiral blowing vortex air flow to form a spirally swirl-blowing air flow, and air surrounded by the blowing air flow being formed in a stable tornado flow and sucked strongly into the air intake port (5).

摘要翻译： 一种进气和吹风装置，其特征在于，包括：吹风扇（11），例如可设置在设置有进气口（5）的主壳体（2）内的全向吹风的涡轮风扇;以及吹风口 （9）包围空气吸入口（5），空气吹出口（9）设置有涡流产生部件，其形成螺旋状的涡流空气流，形成螺旋旋转吹送空气流， 吹气流形成在稳定的龙卷风中并强力吸入进气口（5）。

公开(公告)号：US06201412B1

公开(公告)日：2001-03-13

申请号：US09123902

申请日：1998-07-28

申请人： Toru Iwata ,  Hironori Akamatsu ,  Takashi Hirata

发明人： Toru Iwata ,  Hironori Akamatsu ,  Takashi Hirata

IPC分类号： H03K190175

CPC分类号： H03K19/01707

摘要： The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.

摘要翻译： 本发明的半导体集成电路包括：驱动器，其包括用于驱动负载的MOS晶体管; 以及用于稳定由于MOS晶体管的栅极 - 源极寄生电容而在MOS晶体管的源极处的电压变化的稳定器。

公开(公告)号：US6101441A

公开(公告)日：2000-08-08

申请号：US99526

申请日：1998-06-18

申请人： Toru Iwata

发明人： Toru Iwata

IPC分类号： B60K28/16 ,  F02D29/02 ,  F02D33/00 ,  F02D41/02 ,  F02D41/04 ,  F02D41/30

CPC分类号： F02D41/021 ,  B60K28/16 ,  F02D33/00 ,  F02D41/3076 ,  B60W2710/0622 ,  F02D41/3029

摘要： An engine for a vehicle which selectively performs uniform combustion wherein an air-fuel mixture uniformly spread in the combustion chamber is burnt and stratified combustion wherein an air-fuel mixture converged to a part of the combustion chamber is burnt, is combined with a drive force controller for suppressing a slip of a vehicle drive wheel by reducing the engine output. At the end of drive force reduction control, it is determined whether the engine is in the stratified combustion condition or the uniform combustion condition. When it is in the stratified combustion condition, uniform combustion is first performed for a predetermined time, and then stratified combustion is performed. In this way, the combustion is prevented from becoming instable when the drive force reduction control is terminated.

摘要翻译： 一种用于车辆的发动机，其选择性地执行均匀燃烧，其中在燃烧室中均匀扩散的空气 - 燃料混合物被燃烧并分层燃烧，其中会聚到燃烧室的一部分的空气燃料混合物被燃烧，与驱动力 通过减少发动机输出来抑制车辆驱动轮的滑动的控制器。 在减速控制结束时，确定发动机是处于分层燃烧状态还是均匀燃烧状态。 当处于分层燃烧状态时，首先进行均匀燃烧预定时间，然后进行分层燃烧。 以这种方式，当停止驱动力降低控制时，防止燃烧变得不稳定。

公开(公告)号：US6079511A

公开(公告)日：2000-06-27

申请号：US73938

申请日：1998-05-07

申请人： Toru Iwata

发明人： Toru Iwata

IPC分类号： B60K28/16 ,  F02D29/02 ,  F02D41/02 ,  F02D41/04 ,  F02D41/14 ,  F02D41/30 ,  B60K27/02

CPC分类号： B60K28/16 ,  F02D41/021 ,  F02D41/1475 ,  F02D41/1486 ,  F02D41/3029 ,  F02D41/3076

摘要： In a lean burn engine for a vehicle wherein an ordinary air-fuel ratio and a lean air-fuel ratio are selectively applied, an engine output is reduced when a slip of a drive wheel is detected. By controlling the air-fuel ratio when the engine output is reduced to an ordinary air-fuel ratio, the engine is prevented from becoming unstable even when output is reduced at a lean air -fuel ratio. Preferably, when the engine output reduction has terminated, the air-fuel ratio is returned to the air-fuel ratio prior to the output reduction.

摘要翻译： 在用于车辆的稀燃燃烧发动机中，其中选择性地施加普通空燃比和稀空燃比，当检测到驱动轮的滑动时，发动机输出减小。 通过将发动机输出降低到通常的空燃比来控制空燃比，即使以稀薄的空气 - 燃料比减少输出，也能够防止发动机变得不稳定。 优选地，当发动机输出减少已经终止时，在输出减少之前空燃比返回到空燃比。

公开(公告)号：US6073245A

公开(公告)日：2000-06-06

申请号：US234708

申请日：1999-01-21

申请人： Takashi Hirata ,  Toru Iwata

发明人： Takashi Hirata ,  Toru Iwata

IPC分类号： G06F5/06 ,  G06F1/12

CPC分类号： G06F5/06

摘要： In an output buffer circuit, an input signal is transmitted through a bus by way of a latch circuit and a driver. A stable-state interval detector detects an interval during which the input signal remains in the same logical state. If the stable-state interval detected is relatively short, a drivability controller controls the drivability of the driver at a normal value. To the contrary, if the interval detected is relatively long, the controller increases the drivability of the driver. In general, if the stable-state interval of an input signal is relatively long, then the time taken for the subsequent logical state transition of the signal tends to be longer as compared with a signal having a shorter stable-state interval. However, if the drivability of the driver is increased, then the state transition time is shortened, and substantially equalized with that of a signal having a relatively short stable-state interval. As a result, signal skewing can be minimized.

摘要翻译： 在输出缓冲电路中，输入信号通过一个总线通过一个锁存电路和一个驱动器传输。 稳态区间检测器检测输入信号保持在相同逻辑状态的间隔。 如果检测到的稳态间隔相对较短，则驾驶员控制器将驾驶员的驾驶性能控制在正常值。 相反，如果检测到的间隔相对较长，则控制器增加驾驶员的驾驶性能。 一般来说，如果输入信号的稳态间隔相对较长，则与具有较短稳态间隔的信号相比，信号的后续逻辑状态转换所花费的时间趋于变长。 然而，如果驾驶员的驾驶性能增加，则状态转移时间缩短，并且与具有相对较短的稳态间隔的信号基本相等。 结果，信号偏移可以最小化。

公开(公告)号：US5764566A

公开(公告)日：1998-06-09

申请号：US893682

申请日：1997-07-11

申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

CPC分类号： G11C11/412 ,  G11C11/417

摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。