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102 条记录 (耗时 0.037 秒)

    Test pattern compression for an integrated circuit test environment
    61.
    发明授权
    Test pattern compression for an integrated circuit test environment 有权
    用于集成电路测试环境的测试模式压缩

    公开(公告)号：US06327687B1

    公开(公告)日：2001-12-04

    申请号：US09619985

    申请日：2000-07-20

    申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

    发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

    IPC分类号： G06F1100

    CPC分类号： G01R31/318335 ,  G01R31/318371 ,  G01R31/318547

    摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

    摘要翻译： 一种用于压缩被测电路中扫描链应用的测试图案的方法。 该方法包括生成与扫描链内的扫描单元相关联的符号表达式。 通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。 使用符号仿真，将变量应用于解压缩器以获取符号表达式。 使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。 通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。 求解等式以获得压缩测试图案。

    MODIFYING A FINITE ELEMENT MESH
    62.
    发明申请
    MODIFYING A FINITE ELEMENT MESH 有权

    公开(公告)号：US20220067242A1

    公开(公告)日：2022-03-03

    申请号：US17412637

    申请日：2021-08-26

    申请人： Nilanjan Mukherjee ,  Jean Cabello ,  Jonathan Makem ,  Wafa Daldoul

    发明人： Nilanjan Mukherjee ,  Jean Cabello ,  Jonathan Makem ,  Wafa Daldoul

    IPC分类号： G06F30/23

    摘要： A computer-implemented method of modifying a finite element mesh. The method includes providing an original-input-orphan-mesh, selecting and extracting at least a part of the original-input-orphan-mesh as an orphan-element-patch-object, generating faces on the orphan-element-patch-object as a faces-on-mesh-object geometry, generating a new mesh patch element based on the faces-on-mesh-object-geometry and at least one changed meshing-parameter. The changed meshing-parameter is assigned to generate a new mesh patch element that is different to the corresponding original-input-orphan-mesh. The method further includes generating an amended orphan mesh by replacing the orphan-element-patch-object of the original-input-orphan-mesh by the new mesh patch element.

    Distributed link aggregation group (LAG) for a layer 2 fabric
    63.
    发明授权
    Distributed link aggregation group (LAG) for a layer 2 fabric 有权
    第2层结构的分布式链路聚合组（LAG）

    公开(公告)号：US09497073B2

    公开(公告)日：2016-11-15

    申请号：US13314455

    申请日：2011-12-08

    申请人： Dayavanti G. Kamath ,  Keshav Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

    发明人： Dayavanti G. Kamath ,  Keshav Kamble ,  Dar-Ren Leu ,  Nilanjan Mukherjee ,  Vijoy A. Pandey

    IPC分类号： H04L12/24 ,  H04L12/721 ,  H04L12/709 ,  H04L12/703

    CPC分类号： H04L41/0654 ,  H04L45/245 ,  H04L45/28 ,  H04L45/66 ,  Y02D50/30

    摘要： Each of first and second bridges of a data network having respective links to an external node implement a network bridge component that forwards traffic inside the data network and a virtual bridge component that forwards traffic outside of the data network. A virtual bridge is formed including the virtual bridge components of the first and second bridges and an interswitch link (ISL) between the virtual bridge components of the first and second bridges. Data frames are communicated with each of multiple external network nodes outside the data network via a respective one of multiple link aggregation groups all commonly supported by the virtual bridge.

    摘要翻译： 具有到外部节点的各个链接的数据网络的每个第一和第二桥接器实现转发数据网络内的业务的网桥组件，以及在数据网络之外转发业务的虚拟桥组件。 形成虚拟桥，包括第一和第二桥的虚拟桥组件和第一和第二桥的虚拟桥组件之间的交叉连接（ISL）。 数据帧通过虚拟桥通常支持的多个链路聚合组中的相应一个，与数据网络外部的多个外部网络节点中的每一个进行通信。

    Continuous application and decompression of test patterns and selective compaction of test responses
    65.
    发明授权
    Continuous application and decompression of test patterns and selective compaction of test responses 有权

    公开(公告)号：US08533547B2

    公开(公告)日：2013-09-10

    申请号：US13013712

    申请日：2011-01-25

    申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

    发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318547

    摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

    FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT
    69.
    发明申请
    FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT 审中-公开
    记忆环境中的故障​​诊断

    公开(公告)号：US20110055646A1

    公开(公告)日：2011-03-03

    申请号：US12678747

    申请日：2008-09-18

    申请人： Nilanjan Mukherjee ,  Artur Pogiel ,  Janusz Rajski ,  Jerzy Tyszer

    发明人： Nilanjan Mukherjee ,  Artur Pogiel ,  Janusz Rajski ,  Jerzy Tyszer

    IPC分类号： G11C29/12 ,  G06F11/27

    CPC分类号： G11C29/56 ,  G11C29/40 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/1208

    摘要： Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feed-back structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter (211), a failing column indicator (213), and/or a failing row indicator (214) to collect memory location information for a failing test response.

    摘要翻译： 公开的是用于在存储器内置自检环境中暂时压缩失败存储器测试的测试响应签名的方法和设备，以提供即使在多个时间相关存储器的检测中进行存储器内置自检操作的能力 测试失败。 在本发明的一些实施方案中，将压实的测试响应签名与存储器位置信息一起提供给自动测试设备设备。 根据本发明的各种实施方式，具有嵌入式存储器（204）和存储器BIST控制器（206）的集成电路还包括用作签名寄存器的线性反馈结构（410），其可以临时压缩来自 在内存测试的测试步骤中的嵌入式存储器阵列。 在各种实现中，集成电路还可以包括故障字计数器（211），故障列指示器（213）和/或故障行指示器（214），以收集故障测试响应的存储器位置信息。

    Scan Test Application Through High-Speed Serial Input/Outputs
    70.
    发明申请
    Scan Test Application Through High-Speed Serial Input/Outputs 有权
    通过高速串行输入/输出进行扫描测试应用

    公开(公告)号：US20100313089A1

    公开(公告)日：2010-12-09

    申请号：US12506250

    申请日：2009-07-20

    申请人： Janusz Rajski ,  Nilanjan Mukherjee ,  Mark A. Kassab ,  Thomas H. Rinderknecht ,  Mohamed Dessouky

    发明人： Janusz Rajski ,  Nilanjan Mukherjee ,  Mark A. Kassab ,  Thomas H. Rinderknecht ,  Mohamed Dessouky

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/318547

    摘要： Methods and devices for using high-speed serial links for scan testing are disclosed. The methods can work with any scheme of scan data compression or with uncompressed scan testing. The protocol and hardware to support high speed data transfer reside on both the tester and the device under test. Control data may be transferred along with scan data or be partially generated on chip. Clock signals for testing may be generated on chip as well. In various implementations, the SerDes (Serializer/Deserializer) may be shared with other applications. The Aurora Protocol may be used to transport industry standard protocols. To compensate for effects of asynchronous operation of a conventional high-speed serial link, buffers may be used. The high-speed serial interface may use a data conversion block to drive test cores.

    摘要翻译： 公开了使用高速串行链路进行扫描测试的方法和装置。 这些方法可以使用任何扫描数据压缩或未压缩扫描测试方案。 支持高速数据传输的协议和硬件位于测试仪和被测设备上。 控制数据可以与扫描数据一起传输或者在芯片上部分产生。 用于测试的时钟信号也可以在芯片上生成。 在各种实现中，SerDes（串行器/解串器）可以与其他应用共享。 极光协议可用于传输行业标准协议。 为了补偿常规高速串行链路的异步操作的效果，可以使用缓冲器。 高速串行接口可以使用数据转换块来驱动测试核心。