公开(公告)号：USD686175S1

公开(公告)日：2013-07-16

申请号：US29416224

申请日：2012-03-20

Applicant: Alexander I. Gurary ,  Keng Moy ,  Paul Chang

Designer： Alexander I. Gurary ,  Keng Moy ,  Paul Chang

公开(公告)号：US20130156776A1

公开(公告)日：2013-06-20

申请号：US13435932

申请日：2012-03-30

Applicant: Paul Chang ,  Sejal . Vyas ,  Anthony Leung ,  Phillip A. Sharp

Inventor： Paul Chang ,  Sejal . Vyas ,  Anthony Leung ,  Phillip A. Sharp

IPC: A61K38/47 ,  A61K31/713 ,  A61K39/395 ,  C12Q1/68 ,  C07H21/02 ,  C12N15/113 ,  G01N33/68 ,  A61K38/45 ,  C07K16/40

CPC classification number: C12N15/1137 ,  A61K31/713 ,  A61K38/45 ,  A61K38/47 ,  A61K39/395 ,  A61K39/3955 ,  C07H21/02 ,  C07K16/40 ,  C12N15/113 ,  C12N2310/14 ,  C12N2320/12 ,  C12Q1/6886 ,  G01N33/6893 ,  G01N2333/91142 ,  G01N2500/02

Abstract: The invention provides methods for treating or decreasing the likelihood of developing a stress-granule related disorder and/or cancer by administering one or more poly-ADP-ribose polymerase (PARP) inhibitors, one or more PARP activators, one or more poly-ADP-ribose glycosylase (PARG) activators, and/or one or more poly-ADP-ribose glycohydrolase ARH3 activators. The invention also provides corresponding methods of decreasing stress granule formation and/or proliferation in a cell or a population of cells. The invention further provides methods of increasing the number of stress granules and proliferation in a cell or a population of cells by administering one or more PARP activators, one or more PARP inhibitors, one or more PARG inhibitors, and/or one or more ARH3 inhibitors. The invention also provides methods for screening for agents for treating or decreasing the likelihood of developing a stress granule-related disorder or cancer, and methods for determining the propensity for developing a stress granule-related disorder or cancer, as well as compositions and kits containing one or more PARP inhibitors, one or more PARP activators, one or more PARG activators, and one or more ARH3 activators.

Abstract translation: 本发明提供了通过施用一种或多种聚ADP-核糖聚合酶（PARP）抑制剂，一种或多种PARP激活剂，一种或多种聚ADP来治疗或降低发展应激颗粒相关病症和/或癌症的可能性的方法 核糖糖酵解酶（PARG）激活剂和/或一种或多种聚ADP-核糖糖水解酶ARH3激活剂。 本发明还提供减少细胞或细胞群体中应激颗粒形成和/或增殖的相应方法。 本发明还提供了通过施用一种或多种PARP激活剂，一种或多种PARP抑制剂，一种或多种PARG抑制剂和/或一种或多种ARH3抑制剂来增加细胞或细胞群体中的应激颗粒数量和增殖的方法 。 本发明还提供筛选用于治疗或降低发展应激颗粒相关病症或癌症的可能性的药剂的方法，以及用于确定发展应激颗粒相关病症或癌症倾向的方法，以及含有 一种或多种PARP抑制剂，一种或多种PARP活化剂，一种或多种PARG活化剂和一种或多种ARH3活化剂。

公开(公告)号：US08466451B2

公开(公告)日：2013-06-18

申请号：US13316515

申请日：2011-12-11

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: H01L29/06 ,  H01L31/00 ,  H01L27/105 ,  H01L27/148

CPC classification number: H01L27/1203 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract translation: 提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区 掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。

公开(公告)号：US08435961B2

公开(公告)日：2013-05-07

申请号：US12821967

申请日：2010-06-23

Applicant: Paul Chang ,  Anthony Leung ,  Phillip A. Sharp

Inventor： Paul Chang ,  Anthony Leung ,  Phillip A. Sharp

IPC: A61K31/70 ,  A61K31/00 ,  A61K39/395

CPC classification number: C12N15/111 ,  C07K2319/61 ,  C12N9/1077 ,  C12N15/1137 ,  C12N2310/14 ,  C12N2320/50

Abstract: The invention provides methods for increasing the activity of an inhibitory RNA (RNAi) in a subject requiring administering one or more poly-ADP-ribose polymerase (PARP) inhibitors and/or one or more PARG activators to the subject. The invention also provides methods for increasing the activity of an inhibitory RNA in a cell or cell population requiring contacting a cell or cell population with one or more PARP inhibitors and/or one or more PARG activators. The invention further provides compositions and kits containing one or more PARP inhibitors and/or one or more PARG activators.

Abstract translation: 本发明提供了在需要给受试者施用一种或多种聚ADP-核糖聚合酶（PARP）抑制剂和/或一种或多种PARG活化剂的受试者中提高抑制性RNA（RNAi）的活性的方法。 本发明还提供了增加细胞或细胞群体中抑制性RNA的活性的方法，其需要使细胞或细胞群体与一种或多种PARP抑制剂和/或一种或多种PARG活化剂接触。 本发明还提供了含有一种或多种PARP抑制剂和/或一种或多种PARG活化剂的组合物和试剂盒。

公开(公告)号：US08422273B2

公开(公告)日：2013-04-16

申请号：US12470159

申请日：2009-05-21

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: G11C11/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

Abstract translation: 提供了基于纳米线的场效应晶体管（FET）及其制造技术。 在一个方面，提供了一种FET，其具有在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源区和漏区的多个纳米线通道，其中一个或多个 的器件层被配置为具有来自一个或多个其它器件层的不同阈值电压; 以及围绕纳米线通道的每个器件层共用的栅极。

公开(公告)号：US20120326127A1

公开(公告)日：2012-12-27

申请号：US13169542

申请日：2011-06-27

Applicant: Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

Inventor： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

IPC: H01L51/10 ,  H01L51/40

CPC classification number: H01L29/66045 ,  H01L51/055

Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.

Abstract translation: 一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。 一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。 通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。 一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。 然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。 独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。

公开(公告)号：US20120138888A1

公开(公告)日：2012-06-07

申请号：US13316515

申请日：2011-12-11

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: H01L27/088 ,  H01L29/775 ,  B82Y99/00

CPC classification number: H01L27/1203 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract translation: 提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区 掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。

公开(公告)号：US08051346B2

公开(公告)日：2011-11-01

申请号：US12392468

申请日：2009-02-25

Applicant: Senthil Somasundaram ,  Jun Qian ,  Paul Chang ,  Thomas A. Hamilton

Inventor： Senthil Somasundaram ,  Jun Qian ,  Paul Chang ,  Thomas A. Hamilton

IPC: G01R31/28 ,  G01R31/08 ,  G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G11C7/00 ,  G11C29/00

CPC classification number: G01R31/31716 ,  G01R31/31706 ,  G01R31/31717

Abstract: Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.

Abstract translation: 描述了与可编程应用专用集成电路（ASIC）故障注入相关联的系统，方法和其他实施例。 一个示例性ASIC包括串行器解串器（SERDES）。 示例ASIC还可以包括用于处理ASIC中的数据的逻辑。 至少有一个逻辑可以从SERDES接收数据和/或向SERDES提供数据。 示例性ASIC还可以包括嵌入式故障注入逻辑（EFIL），以控制将故障注入与至少一个逻辑相关联的路径（例如，数据，控制）。 示例性ASIC还可以包括由EFIL控制的嵌入式多路复用器集合（ESOM）。 ESOM可由EFIL控制，以将故障信号注入数据通路。

公开(公告)号：US20110097328A1

公开(公告)日：2011-04-28

申请号：US12821967

申请日：2010-06-23

Applicant: Paul Chang ,  Anthony Leung ,  Phillip A. Sharp

Inventor： Paul Chang ,  Anthony Leung ,  Phillip A. Sharp

IPC: A61K39/395 ,  A61K31/7088 ,  C12N5/02

CPC classification number: C12N15/111 ,  C07K2319/61 ,  C12N9/1077 ,  C12N15/1137 ,  C12N2310/14 ,  C12N2320/50

Abstract: The invention provides methods for increasing the activity of an inhibitory RNA (RNAi) in a subject requiring administering one or more poly-ADP-ribose polymerase (PARP) inhibitors and/or one or more PARG activators to the subject. The invention also provides methods for increasing the activity of an inhibitory RNA in a cell or cell population requiring contacting a cell or cell population with one or more PARP inhibitors and/or one or more PARG activators. The invention further provides compositions and kits containing one or more PARP inhibitors and/or one or more PARG activators.

Abstract translation: 本发明提供了在需要给受试者施用一种或多种聚ADP-核糖聚合酶（PARP）抑制剂和/或一种或多种PARG活化剂的受试者中提高抑制性RNA（RNAi）的活性的方法。 本发明还提供了增加细胞或细胞群体中抑制性RNA的活性的方法，其需要使细胞或细胞群体与一种或多种PARP抑制剂和/或一种或多种PARG活化剂接触。 本发明还提供了含有一种或多种PARP抑制剂和/或一种或多种PARG活化剂的组合物和试剂盒。

公开(公告)号：US20100295021A1

公开(公告)日：2010-11-25

申请号：US12470128

申请日：2009-05-21

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: H01L29/15 ,  H01L21/336 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract translation: 提供基于纳米线的设备。 一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。