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公开(公告)号：US08216902B2
公开(公告)日：2012-07-10
申请号：US12536741
申请日：2009-08-06
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译： 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。
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公开(公告)号：US08084308B2
公开(公告)日：2011-12-27
申请号：US12470128
申请日：2009-05-21
IPC分类号： H01L21/00 , H01L21/84 , H01L27/148 , H01L27/105
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译： 提供基于纳米线的设备。 一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。
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公开(公告)号：US20110031473A1
公开(公告)日：2011-02-10
申请号：US12536741
申请日：2009-08-06
IPC分类号： H01L27/11 , H01L29/66 , H01L21/8239
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译： 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。
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公开(公告)号：US20120168872A1
公开(公告)日：2012-07-05
申请号：US13417829
申请日：2012-03-12
IPC分类号： H01L27/088 , B82Y99/00
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译： 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。
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公开(公告)号：US08466451B2
公开(公告)日：2013-06-18
申请号：US13316515
申请日：2011-12-11
IPC分类号： H01L29/06 , H01L31/00 , H01L27/105 , H01L27/148
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译： 提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区 掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。
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公开(公告)号：US08422273B2
公开(公告)日：2013-04-16
申请号：US12470159
申请日：2009-05-21
IPC分类号： G11C11/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
摘要翻译： 提供了基于纳米线的场效应晶体管（FET）及其制造技术。 在一个方面，提供了一种FET，其具有在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源区和漏区的多个纳米线通道，其中一个或多个 的器件层被配置为具有来自一个或多个其它器件层的不同阈值电压; 以及围绕纳米线通道的每个器件层共用的栅极。
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公开(公告)号：US20120138888A1
公开(公告)日：2012-06-07
申请号：US13316515
申请日：2011-12-11
IPC分类号： H01L27/088 , H01L29/775 , B82Y99/00
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译： 提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区 掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。
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公开(公告)号：US20100295021A1
公开(公告)日：2010-11-25
申请号：US12470128
申请日：2009-05-21
IPC分类号： H01L29/15 , H01L21/336 , H01L27/12
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译： 提供基于纳米线的设备。 一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。
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公开(公告)号：US08472239B2
公开(公告)日：2013-06-25
申请号：US13467126
申请日：2012-05-09
IPC分类号： G11C11/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
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公开(公告)号：US08395220B2
公开(公告)日：2013-03-12
申请号：US13417829
申请日：2012-03-12
IPC分类号： H01L27/088 , B82Y99/00
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译： 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。
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