公开(公告)号：US08372720B2

公开(公告)日：2013-02-12

申请号：US12679991

申请日：2008-12-09

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/513

摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US08217446B2

公开(公告)日：2012-07-10

申请号：US12559865

申请日：2009-09-15

申请人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.

摘要翻译： 每个存储器串都具有第一半导体层，该第一半导体层具有相对于衬底在垂直方向上延伸的一对柱状部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕电荷存储层的第一导电层。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 形成为围绕所述第二半导体层的侧表面的栅极绝缘层; 以及形成为围绕所述栅极绝缘层的第二导电层。 第二半导体层的有效杂质浓度小于或等于第一半导体层的有效杂质浓度。

公开(公告)号：US08198667B2

公开(公告)日：2012-06-12

申请号：US12808321

申请日：2008-12-25

申请人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

摘要： A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

摘要翻译： 通过在硅衬底上交替层叠多个电介质膜和电极膜来形成层叠体。 接下来，在层叠体中形成在层叠方向上延伸的贯通孔。 接下来，进行选择性氮化处理，以在对应于电极膜的通孔的内表面的区域中选择性地形成由氮化硅制成的电荷层。 接下来，进行高压氧化处理以在电荷层和电极膜之间形成由氧化硅制成的阻挡层。 接下来，在通孔的内侧表面上形成由氧化硅制成的隧道层。 因此，可以制造其中为每个电极膜分裂电荷层的快闪存储器。

公开(公告)号：US08154068B2

公开(公告)日：2012-04-10

申请号：US12647836

申请日：2009-12-28

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kidoh ,  Yoshiaki Fukuzumi

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kidoh ,  Yoshiaki Fukuzumi

IPC分类号： H01L29/76

CPC分类号： H01L27/11578 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer formed to surround a side surface of the first semiconductor layer; and a first conductive layer formed to surround a side surface of the electric charge accumulation layer. The columnar portions are aligned at a first pitch in a first direction orthogonal to the vertical direction, and arranged in a staggered pattern at a second pitch in a second direction orthogonal to the vertical and first directions. The first conductive layers are configured to be arranged at the first pitch in the first direction, and extend to curve in a wave-like fashion in the second direction along the staggered-pattern arrangement.

摘要翻译： 每个存储串包括：第一半导体层，具有在垂直方向上延伸到基板的一对柱状部分和形成为连接该一对柱状部分的下端的接合部分; 形成为包围第一半导体层的侧面的电荷蓄积层; 以及形成为围绕电荷蓄积层的侧表面的第一导电层。 柱状部分在垂直于垂直方向的第一方向上以第一间距排列，并且在垂直于垂直方向和第一方向的第二方向上以第二间距布置成交错图案。 第一导电层被配置为沿着第一方向以第一间距布置，并且沿着交错图案布置在第二方向上以波浪形的方式延伸。

公开(公告)号：US08048798B2

公开(公告)日：2011-11-01

申请号：US12389977

申请日：2009-02-20

申请人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/4763

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so that the semiconductor layer infills the first hole and the second hole after the removal of the sacrificing layer.

摘要翻译： 一种制造非易失性半导体存储装置的方法，包括：形成第一导电层，使其通过第一绝缘层沿上下方向夹持; 形成第一孔，使其穿透第一绝缘层和第一导电层; 在面向所述第一孔的侧壁上形成第一侧壁绝缘层; 形成牺牲层，使牺牲层填充第一孔; 在牺牲层的上层上形成第二导电层，使得第二导电层在上下方向上被第二绝缘层夹持; 在与所述第一孔匹配的位置上形成第二孔，使得所述第二孔穿过所述第二绝缘层和所述第二导电层; 在面向所述第二孔的侧壁上形成第二侧壁绝缘层; 在形成第二侧壁绝缘层之后去除牺牲层; 以及形成半导体层，使得半导体层在去除牺牲层之后填充第一孔和第二孔。

公开(公告)号：US08013383B2

公开(公告)日：2011-09-06

申请号：US12389856

申请日：2009-02-20

申请人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Akihiro Nitayama ,  Hitoshi Ito ,  Yasuyuki Matsuoka

发明人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Akihiro Nitayama ,  Hitoshi Ito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792

CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.

摘要翻译： 非易失性半导体存储装置具有串联连接多个电可重写存储单元的多个存储串。 存储器串具有在垂直于衬底的方向上延伸的柱状半导体层; 形成为与柱状半导体层配合地夹着电荷存储层的导电层; 以及形成为与导电层的顶面接触的金属层。

公开(公告)号：US20100276743A1

公开(公告)日：2010-11-04

申请号：US12808321

申请日：2008-12-25

申请人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

摘要： A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

摘要翻译： 通过在硅衬底上交替层叠多个电介质膜和电极膜来形成层叠体。 接下来，在层叠体中形成在层叠方向上延伸的贯通孔。 接下来，进行选择性氮化处理，以在对应于电极膜的通孔的内表面的区域中选择性地形成由氮化硅制成的电荷层。 接下来，进行高压氧化处理，以在电荷层和电极膜之间形成由氧化硅制成的阻挡层。 接下来，在通孔的内侧表面上形成由氧化硅制成的隧道层。 因此，可以制造其中为每个电极膜分裂电荷层的快闪存储器。

公开(公告)号：US20100118610A1

公开(公告)日：2010-05-13

申请号：US12610703

申请日：2009-11-02

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A stacked body with a plurality of dielectric films and electrode films alternately stacked therein is provided. The electrode film is divided into a plurality of control gate electrodes extending in one direction. The stacked body is provided with a U-pillar penetrating through the select gate electrodes and the control gate electrodes, having one end connected to a source line, and having the other end connected to a bit line. Moreover, a different potential is applied to uppermost one of the control gate electrodes than that applied to the other control gate electrodes.

摘要翻译： 提供了具有交替层叠的多个电介质膜和电极膜的层叠体。 电极膜被分成沿一个方向延伸的多个控制栅电极。 层叠体设置有穿过选择栅极和控制栅电极的U柱，其一端连接到源极线，并且另一端连接到位线。 此外，与施加到其他控制栅电极相比，控制栅电极的最上一个施加不同的电位。

公开(公告)号：US20100038699A1

公开(公告)日：2010-02-18

申请号：US12542276

申请日：2009-08-17

申请人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured.

摘要翻译： 通过交替堆叠多个绝缘膜和多个电极膜，在硅基板上形成层叠体，并且形成贯通孔，以在层叠方向上延伸。 接下来，通过通孔蚀刻绝缘膜，在电极膜之间形成间隙。 电荷存储层沿着通孔的侧面和间隙的内表面形成，硅柱填充到通孔中。 由此，制造非易失性半导体存储器件。

公开(公告)号：US20100034028A1

公开(公告)日：2010-02-11

申请号：US12536226

申请日：2009-08-05

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： G11C7/00 ,  G11C16/02 ,  G11C16/26

CPC分类号： H01L27/11578 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device having n (n is an integer of two or more) electrode films stacked and having charge storage layers provided above and below each of the electrode films, when data “0” is written by injecting electrons into the charge storage layer on a source line side of a memory cell of the number k (k is an integer of 1 to (n−1)) as counted from an end on a bit line side in a selected semiconductor pillar, positive program potential is given to the electrode film of the number 1 to k as counted from the bit line side, and 0 V is given to the electrode film of the number (k+1) to n, therewith positive potential is given to the bit line and 0 V is given to the source line.

摘要翻译： 在具有n（n为2以上的整数）的电极膜的非易失性半导体存储装置中，在各电极膜的上下配置有电荷存储层的情况下，在将数据“0”注入到电荷存储部 在选择的半导体柱中从位线侧的端部开始计数k（k为1〜（n-1）的整数）的存储单元的源极侧的层，将正的程序电位赋予 从位线侧计数1〜k的电极膜，向数字（k + 1）〜n的电极膜施加0V，其中给定位线为0V，0V为 给源线。