公开(公告)号：US20120197583A1

公开(公告)日：2012-08-02

申请号：US13290143

申请日：2011-11-07

Applicant: HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  PO-CHUAN HSIEH ,  YU-CHANG PAI ,  SHOU-KUO HSU

Inventor： HSIEN-CHUAN LIANG ,  SHEN-CHUN LI ,  PO-CHUAN HSIEH ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC: G06F19/00

CPC classification number: G01R31/2801 ,  G01R31/2812 ,  G01R31/2834

Abstract: A method of testing a printed circuit board (PCB) acquires test points from a wiring diagram of the PCB. Frequency domain tested items for each test point and a standard value of each frequency domain tested item are preset. A distance between a preset fiducial point and each test point is computed to create a testing order of the test points according to the distances. The frequency domain tested items of each test point are computed according to the testing order. A pass or a failure of each test point is displayed according to a determination of if each of the computed frequency domain tested items within the corresponding standard value, and a test result of the PCB is output according to the passes or the failures.

Abstract translation: 测试印刷电路板（PCB）的方法从PCB接线图获取测试点。 每个测试点的频域测试项目和每个频域测试项目的标准值都是预设的。 计算预设基准点与每个测试点之间的距离，以根据距离创建测试点的测试顺序。 每个测试点的频域测试项目根据测试顺序计算。 根据是否根据通过或故障输出每个计算出的频域测试项目在相应的标准值内以及PCB的测试结果的确定来显示每个测试点的通过或失败。

公开(公告)号：US20120185819A1

公开(公告)日：2012-07-19

申请号：US13244625

申请日：2011-09-25

Applicant: ZHENG SHAN ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： ZHENG SHAN ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.

Abstract translation: 在使用计算装置验证印刷电路板（PCB）布局的方法中，从计算装置的存储装置获得PCB模拟文件，并且根据PCB仿真文件在显示装置上显示PCB图像。 PCB图像包括多个信号线和开关电压调节器节点（SVRN）。 从PCB图像中选择要检查的SVRN，并搜索SVRN周围的所有信号线。 该方法计算所选择的SVRN与所搜索的信号线之间的布局距离，并且生成图形窗口界面以定位其布局距离等于或小于最小距离的信号线。 该方法通过将布局距离增加到最小距离来进一步修改定位信号线的布局以满足布局设计规范。

公开(公告)号：US20120185097A1

公开(公告)日：2012-07-19

申请号：US13211324

申请日：2011-08-17

Applicant: SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  SHOU-KUO HSU

Inventor： SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  SHOU-KUO HSU

IPC: B25J9/10

CPC classification number: B25J9/1679 ,  G05B19/4015

Abstract: A computer determines a first origin of a first coordinate system of a PCB, and controls a robotic arm to position a probe above the first origin. Furthermore, the computer determines a second origin of a second coordinate system of the robotic arm, and determines displacement values from the first origin to a test point in controlling movements of the robotic arm in the second coordinate system. A graph representing the test point is recognized in an image of the PCB, pixel value differences between the graph center and the image center are determined and converted to displacement correction values for controlling the movements of the robotic arm and determining 3D coordinates of the test point. The robotic arm is moved along a Z-axis of the second coordinate system to precisely position the probe on the test point of the PCB.

Abstract translation: 计算机确定PCB的第一坐标系的第一原点，并且控制机器人臂将探针定位在第一原点上方。 此外，计算机确定机器人手臂的第二坐标系的第二原点，并且在控制机器人手臂在第二坐标系中的运动中确定从第一原点到测试点的位移值。 在PCB的图像中识别表示测试点的图形，并且确定图形中心和图像中心之间的像素值差异并将其转换为用于控制机器人手臂的运动并确定测试点的3D坐标的位移校正值 。 机器人臂沿着第二坐标系的Z轴移动，以将探头精确地定位在PCB的测试点上。

公开(公告)号：US20120167027A1

公开(公告)日：2012-06-28

申请号：US13172858

申请日：2011-06-30

Applicant: YA-LING HUANG ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： YA-LING HUANG ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: An electronic device and a method for checking layout distance of a printed circuit board (PCB) including presetting a checking condition to determine a reference layer. A high speed signal path is selected from a PCB design file, and a layer where the selected high speed signal path is located can be determined A reference layer of the determined layer is determined according to the checking condition, and a split line of the reference layer is determined. A shortest distance between each segment of the selected high speed signal path and the split line is calculated. If the shortest distance between a segment and the split line is less than the standard distance, layout of the segment is determined to be invalid.

Abstract translation: 一种用于检查印刷电路板（PCB）的布局距离的电子设备和方法，包括预设检查条件以确定参考层。 可以从PCB设计文件中选择高速信号路径，并且可以确定所选择的高速信号路径所在的层。根据检查条件确定确定层的参考层，并且确定参考的分割线 层被确定。 计算所选择的高速信号路径的每个段与分割线之间的最短距离。 如果段与分割线之间的最短距离小于标准距离，则段的布局被确定为无效。

公开(公告)号：US20120048610A1

公开(公告)日：2012-03-01

申请号：US12875156

申请日：2010-09-03

Applicant: SHOU-KUO HSU ,  YUNG-CHIEH CHEN ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  SHEN-CHUN LI ,  CHIA-NAN PAI

Inventor： SHOU-KUO HSU ,  YUNG-CHIEH CHEN ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  SHEN-CHUN LI ,  CHIA-NAN PAI

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/115 ,  H05K2201/09836 ,  Y10T428/24917

Abstract: A printed circuit board (PCB) includes two layers, two signal transmission traces, and a vertical interconnect access (via). The signal transmission traces are respectively arranged on the layers. The signal transmission traces are electrically connected to each other through the via. A centerline of the via with a vertical line of the layers form an acute angle θ, the angle θ is less than cos−1[(Lv2−Lt2)/(Lv2+Lt2)]. Wherein Lt is loss of the two signal transmitting traces in a unit length, and Lv is loss of the via in a unit length.

Abstract translation: 印刷电路板（PCB）包括两层，两条信号传输路径和一条垂直互连接口（via）。 信号传输迹线分别布置在层上。 信号传输迹线通过通孔彼此电连接。 具有垂直线的通孔的中心线形成锐角和角度;角度和角度; 小于cos-1 [（Lv2-Lt2）/（Lv2 + Lt2）]。 其中Lt是以单位长度丢失两个信号传输迹线，并且Lv是单位长度中的通孔的损失。

公开(公告)号：US20120032385A1

公开(公告)日：2012-02-09

申请号：US12981544

申请日：2010-12-30

Applicant: SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  YUNG-CHIEH CHEN ,  YU-CHANG PAI ,  SHOU-KUO HSU

Inventor： SHEN-CHUN LI ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  YUNG-CHIEH CHEN ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC: B25B5/06

CPC classification number: B25B11/00 ,  B25B1/2421 ,  B25J15/106

Abstract: A clamping mechanism for holding a workpiece includes an end executor, a driving member, and a contact member detachably mounted on the end executor. The end executor includes a plurality of claws arranged in matrix. The contact member includes a mounting board and a plurality of contact sleeves corresponding to the claws. The driving member is capable of driving the mounting board, moving the contact sleeves to extend the claws, and hold the workpiece.

Abstract translation: 用于保持工件的夹持机构包括端部执行器，驱动构件和可拆卸地安装在端部执行器上的接触构件。 末端执行器包括排列成矩阵的多个爪。 接触构件包括安装板和对应于爪的多个接触套筒。 驱动构件能够驱动安装板，移动接触套以延伸爪并且保持工件。

公开(公告)号：US20120016920A1

公开(公告)日：2012-01-19

申请号：US13038386

申请日：2011-03-02

Applicant: WEN-LAING TSENG ,  SHEN-CHUN LI ,  YU-CHANG PAI ,  SHOU-KUO HSU

Inventor： WEN-LAING TSENG ,  SHEN-CHUN LI ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC: G06F1/02 ,  G06F17/16

CPC classification number: G06F17/5036

Abstract: A direct current compensation method for S-parameter rational functions reads S-parameters f(sk), which are generated at given frequency sk, from a storage unit. An S-parameter, which is generated at frequency sk=0 is supplemented into the S-parameters f(sk), upon the condition that there is no S-parameter which is generated at the frequency sk=0. An S-parameter ration function is generated according to the S-parameters f(sk). A DC level of the S-parameter rational function is compensated to generate a compensated S-parameter rational function.

Abstract translation: S参数有理函数的直流补偿方法从存储单元读取以给定频率sk生成的S参数f（sk）。 在频率sk = 0处生成的S参数在没有在频率sk = 0处生成的S参数的条件下，将在频率sk = 0处生成的S参数补充到S参数f（sk）中。 根据S参数f（sk）生成S参数比例函数。 S参数有理函数的直流电平被补偿以产生补偿的S参数有理函数。

公开(公告)号：US20110266046A1

公开(公告)日：2011-11-03

申请号：US12841125

申请日：2010-07-21

Applicant: PO-CHUAN HSIEH ,  YU-CHANG PAI ,  CHIEN-HUNG LIU ,  SHOU-KUO HSU

Inventor： PO-CHUAN HSIEH ,  YU-CHANG PAI ,  CHIEN-HUNG LIU ,  SHOU-KUO HSU

IPC: H05K9/00

CPC classification number: H05K9/0041 ,  H05K9/0024

Abstract: An enclosure of an electronic device includes a plate. The plate defines a number of through holes. A number of shields extend from the plate corresponding to the through holes. Each shield extends outwards from the outer surface of the plate, surrounding and partly covering a corresponding through hole. The enclosure with the shields can shield the electronic device from EMI.

Abstract translation: 电子设备的外壳包括板。 该板限定了多个通孔。 多个屏蔽件从对应于通孔的板延伸。 每个护罩从板的外表面向外延伸，围绕并部分覆盖相应的通孔。 带屏蔽的外壳可以屏蔽电子设备免受EMI影响。

公开(公告)号：US20110214099A1

公开(公告)日：2011-09-01

申请号：US12884204

申请日：2010-09-17

Applicant: YUNG-CHIEH CHEN ,  SHOU-KUO HSU

Inventor： YUNG-CHIEH CHEN ,  SHOU-KUO HSU

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: In a method and system for automatically generating a circuit diagram for a wiring design of a circuit board, a preset output format of wiring attributes of the wiring design for the circuit board is received. A board file is created. Initial parameters of the wiring design for the circuit board are preset. The wiring attributes of the wiring design are determined by simulating and analyzing the wiring design, and be backed up into a document. The wiring attributes are imported into the board file according to the preset output format. A circuit diagram is generated according to the wiring design and the initial parameters, and is adjusted using the wiring attributes in the board file.

Abstract translation: 在用于自动生成电路板的布线设计的电路图的方法和系统中，接收用于电路板的布线设计的布线属性的预设输出格式。 创建一个板文件。 预置电路板接线设计的初始参数。 接线设计的接线属性是通过仿真和分析接线设计来确定的，并被备份到一个文件中。 接线属性根据预设的输出格式导入电路板文件。 根据接线设计和初始参数生成电路图，并使用板文件中的接线属性进行调整。

公开(公告)号：US20110094782A1

公开(公告)日：2011-04-28

申请号：US12647395

申请日：2009-12-25

Applicant: HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: H05K1/16

CPC classification number: H05K1/0253 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8  Wpad + 10  T 0.8  Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.

Abstract translation: 印刷电路板包括信号平面和参考平面。 信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。 参考平面为通过无源元件和信号传输线传输的信号提供返回路径。 在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。 垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8 Wpad + 10 T T W W W T T T + T，其中W pad是焊盘的宽度，Wtrace是 传输线的宽度，T是焊盘的高度。