公开(公告)号：US11018444B2

公开(公告)日：2021-05-25

申请号：US16033141

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Fred Worley

IPC: H05K1/18 ,  H05K3/30 ,  H01R12/73 ,  H01R12/72 ,  H01R43/20 ,  H01R43/26

Abstract: In an example, a device includes: a printed circuit board (PCB); at least one solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) mounted on the PCB at a second side of the PCB; and at least one connector attached to the PCB at a third side of the PCB, wherein the device is configured to operate in a first speed from a plurality of operating speeds based on a first input received via the at least one connector.

公开(公告)号：US11016682B2

公开(公告)日：2021-05-25

申请号：US16431539

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/42

Abstract: A memory device is configured to communicate with one or more external devices, the memory device including a configurable bit or a mode select pin for determining which one of two or more different communication protocols that the memory device uses to communicate with the one or more external devices, wherein the two or more different communications protocols include at least a Controller Area Network (CAN) protocol and a System Management Bus (SMBus) protocol.

公开(公告)号：US11003229B2

公开(公告)日：2021-05-11

申请号：US16111167

申请日：2018-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Ramdas P Kachare ,  Wentao Wu

IPC: G06F1/30 ,  G06F1/28 ,  G06F3/06

Abstract: A system is disclosed that provides emergency backup power to a solid-state drive (SSD) that may not contain any internal supercapacitors. The SSD may include a first connector and a hold-up power supply. The first connector may have a predetermined form factor and may being capable of being connected to a corresponding connector of a midplane of a storage system. The first connector may include a main power connection that is connected to a main power supply of the midplane if the first connector is connected to the corresponding connector of the midplane. The hold-up power supply may be internal to the SSD, and may receive hold-up energy from an external energy source for a predetermined amount of time after the first connector has been disconnected from the main power connection of the midplane so that the SSD may store any host data write requests that the SSD has acknowledged.

公开(公告)号：US10963394B2

公开(公告)日：2021-03-30

申请号：US16012470

申请日：2018-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. Kachare ,  Sompong Paul Olarig ,  Vikas Sinha ,  Zvika Guz

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/109 ,  G06F3/06 ,  G06N20/00

Abstract: A controller of a data storage device includes: a host interface providing an interface to a host computer; a flash translation layer (FTL) translating a logical block address (LBA) to a physical block address (PBA) associated with an input/output (I/O) request; a flash interface providing an interface to flash media to access data stored on the flash media; and one or more deep neural network (DNN) modules for predicting an I/O access pattern of the host computer. The one or more DNN modules provide one or more prediction outputs to the FTL that are associated with one or more past I/O requests and a current I/O request received from the host computer, and the one or more prediction outputs include at least one predicted I/O request following the current I/O request. The FTL prefetches data stored in the flash media that is associated with the at least one predicted I/O request.

公开(公告)号：US20210089102A1

公开(公告)日：2021-03-25

申请号：US17112933

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. Kachare ,  Wentao Wu ,  Sompong Paul Olarig

IPC: G06F1/28 ,  G06F1/30 ,  G06F1/26 ,  G06F1/3225 ,  G06F11/20 ,  G06F11/30 ,  G06F11/34 ,  G06F1/3287

Abstract: A storage system comprises one or more storage devices, power supplies supplying power to the storage device, a processor that performs in response to determining that the total power consumption of the one or more storage devices is less than a first percentage threshold of a load of the active power supplies, deactivating one or more of the active power supplies until the total power consumption is equal to or greater than the first percentage threshold of a load of each of the active power supplies, and in response to determining that the total power consumption is equal to or greater than a second percentage threshold of a load of each of the active power supplies, activating one or more of the deactivated ones of the power supplies until the total power consumption is less than the second percentage threshold of the load of each of the active power supplies.

公开(公告)号：US10824348B2

公开(公告)日：2020-11-03

申请号：US15275337

申请日：2016-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Mu-Tien Chang

IPC: G06F3/06 ,  G06F21/60 ,  G06F21/62 ,  G06F21/79

Abstract: A secure memory (145) is disclosed. The memory (145) may include data storage (310, 315, 320, 325, 330, 335, 340, 345) for data, along with a data read logic (405) and a data write logic (410) to read and write data from the data storage (310, 315, 320, 325, 330, 335, 340, 345). A password storage (355) may store a stored password (510). A receiver may receive a received password (505) from a memory controller (205). A comparator may compare the received password (505) with the stored password (510). An erase logic (435) may erase data in the data storage (310, 315, 320, 325, 330, 335, 340, 345) if the received password (505) does not match the stored password (510). Finally, a block logic (425) may block access to the memory (145) from the memory controller (205) until after the comparator (430) completes its operation.

公开(公告)号：US10762032B2

公开(公告)日：2020-09-01

申请号：US16565358

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig

IPC: G06F13/10 ,  G06F13/42 ,  G06F13/16

Abstract: An adaptive interface high availability storage device. In some embodiments, the adaptive interface high availability storage device includes: a rear storage interface connector; a rear multiplexer, connected to the rear storage interface connector; an adaptable circuit connected to the rear multiplexer; a front multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the front multiplexer. The adaptive interface high availability storage device may be configured to operate in a single-port state or in a dual-port state. The adaptive interface high availability storage device may be configured: in the single-port state, to present a single-port host side storage interface according to a first storage protocol at the rear storage interface connector, and in the dual-port state, to present a dual-port host side storage interface according to the first storage protocol at the rear storage interface connector.

公开(公告)号：US10686833B2

公开(公告)日：2020-06-16

申请号：US15489401

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Son T. Pham ,  Jason Martineau

IPC: H04L29/06 ,  G06F13/40 ,  G06F13/42

Abstract: A computer storage array detects and counters denial of service (DoS) attacks and provides one or more remote initiators with access to one or more storage devices connected to the computer storage array. computer storage array includes: a computer processor configured to run an operating system for managing networking protocols; a networking device configured to monitor and route network traffic, at a packet level to, and from the storage devices; a baseboard management controller (BMC) configured to detect a DoS attack based on monitoring of statistics of the network traffic by the networking device; a PCIe switch connecting the BMC with each of the storage devices via a PCIe bus; and a computer motherboard to which the computer processor, networking device, BMC and PCIe switch are installed.

公开(公告)号：US20200097425A1

公开(公告)日：2020-03-26

申请号：US16696649

申请日：2019-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Stephen G. Fischer ,  Sompong Paul Olarig

IPC: G06F13/28 ,  G06F3/06 ,  G06F13/42

Abstract: An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.

公开(公告)号：US10586043B2

公开(公告)日：2020-03-10

申请号：US15690265

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Ramdas P. Kachare ,  Son T. Pham

IPC: G06F21/56 ,  G06F21/79 ,  G06F21/55 ,  G06F21/57 ,  H04L29/06

Abstract: A system and a method to detect malicious software written to an Ethernet solid-state drive (eSSD). The system includes an Ethernet switch, at least one SSD, and a baseboard management controller (BMC). The Ethernet switch receives write data from a communication network in response to a write command. The at least one SSD receives the write data from the Ethernet switch and stores the received write data. The BMC receives from the at least one SSD the received write data. The BMC determines whether the received write data contains malicious software. The received write data may be contained in a plurality of Ethernet packets in which case the BMC stores the received write data in a scan buffer in an order that is based on an assembled order of the received write data.