公开(公告)号：US11348901B1

公开(公告)日：2022-05-31

申请号：US17106884

申请日：2020-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: A first bonding unit is provided, which includes a first substrate, a first passivation dielectric layer, and first bonding pads. A second bonding unit is provided, which includes a second substrate, a second passivation dielectric layer, and second bonding pads including bonding pillar structures. Solder material portions are formed on physically exposed surfaces of the first bonding pads. The second bonding unit is attached to the first bonding unit by bonding the at least one of the bonding pillar structures to a respective solder material portion.

公开(公告)号：US11282857B2

公开(公告)日：2022-03-22

申请号：US16887738

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Peter Rabkin ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/207 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US11107516B1

公开(公告)日：2021-08-31

申请号：US16798686

申请日：2020-02-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H01L27/1159 ,  G11C11/22 ,  H01L29/16 ,  H01L29/778

Abstract: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.

公开(公告)号：US11088116B2

公开(公告)日：2021-08-10

申请号：US16694438

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/822 ,  H01L27/06 ,  H01L23/00 ,  H01L25/00

Abstract: A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.

公开(公告)号：US11037908B2

公开(公告)日：2021-06-15

申请号：US16521849

申请日：2019-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.

公开(公告)号：US20210065802A1

公开(公告)日：2021-03-04

申请号：US16551553

申请日：2019-08-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C16/30 ,  H03H11/28

Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.

公开(公告)号：US20210050054A1

公开(公告)日：2021-02-18

申请号：US16540862

申请日：2019-08-14

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Peter Rabkin ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

IPC: G11C11/56 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408

Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

公开(公告)号：US20200294909A1

公开(公告)日：2020-09-17

申请号：US16886695

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L27/11582

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

公开(公告)号：US20200143889A1

公开(公告)日：2020-05-07

申请号：US16233780

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

公开(公告)号：US10319680B1

公开(公告)日：2019-06-11

申请号：US15909036

申请日：2018-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun Sel ,  Masaaki Higashitani ,  Mohan Dunga ,  Fumiaki Toyama ,  Peter Rabkin

IPC: H01L23/52 ,  H01L23/532 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582

Abstract: A structure includes a metal interconnect structure embedded in a lower interconnect level dielectric layer overlying a substrate, at least one material layer overlying the metal interconnect structure, a first contact level dielectric layer overlying the at least one material layer; a metal contact via structure vertically extending through the first contact level dielectric layer and the at least one material layer and contacting a top surface of the metal interconnect structure, and an encapsulated tubular cavity laterally surrounding at least a lower portion of the metal contact via structure, and vertically extending through the at least one material layer.