公开(公告)号：US5745431A

公开(公告)日：1998-04-28

申请号：US583263

申请日：1996-01-05

申请人： Dale Edward Pontius ,  Steven William Tomashot ,  Toshiaki Kirihata ,  Robert Henry Kruggel

发明人： Dale Edward Pontius ,  Steven William Tomashot ,  Toshiaki Kirihata ,  Robert Henry Kruggel

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C8/18

摘要： An address decode circuit for receiving address input signals, includes a device for detecting a change in the address input signals, and a device for generating a control signal in response to a detected change in the address input signals. A gating mechanism gates at least one address bit in the address input signals input to the address decode circuit with the control signal.

摘要翻译： 一种用于接收地址输入信号的地址解码电路，包括用于检测地址输入信号变化的装置，以及响应于所检测到的地址输入信号的变化而产生控制信号的装置。 选通机构通过控制信号将输入到地址解码电路的地址输入信号中的至少一个地址位置1。

公开(公告)号：US5745430A

公开(公告)日：1998-04-28

申请号：US777559

申请日：1996-12-30

申请人： Hing Wong ,  Toshiaki Kirihata ,  Bozidar Krsnik

发明人： Hing Wong ,  Toshiaki Kirihata ,  Bozidar Krsnik

IPC分类号： G06F1/06 ,  G01R31/30 ,  G06F1/08 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G01R31/3016

摘要： A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

公开(公告)号：US5619460A

公开(公告)日：1997-04-08

申请号：US477061

申请日：1995-06-07

申请人： Toshiaki Kirihata ,  Hing Wong

发明人： Toshiaki Kirihata ,  Hing Wong

IPC分类号： G11C29/12 ,  G11C29/06 ,  G11C29/10 ,  G11C29/00

CPC分类号： G11C29/10

摘要： A method of testing a RAM. The RAM array is arranged in rows and columns. The rows are grouped into word line groups. The method includes the steps of: a) asserting an array select signal; b) selecting a group of rows in the array; c) selecting at least one row of the selected group of rows; and, d) repeating steps b and c until all of the groups are selected. Array Sense Amps may be set when the first group is selected and remain set until the last group is selected. In one test, word lines in all of the selected rows are activated and remain activated until the final selected row is selected. In a second test, word lines in selected groups are toggled with RAS. If a group contains a known defective word line, that group is either not addressed or its selection is disabled. In each selected group, one row, alternating rows or, all of the rows may be selected.

摘要翻译： 一种测试RAM的方法。 RAM阵列以行和列排列。 行被分组成字线组。 该方法包括以下步骤：a）断言阵列选择信号; b）在数组中选择一组行; c）选择所选择的一组行中的至少一行; 和d）重复步骤b和c，直到选择所有组。 当选择第一组时，可以设置阵列传感放大器，并保持设置，直到选择最后一个组。 在一个测试中，所有选定行中的字线都被激活，并保持激活状态，直到选中最后一行。 在第二个测试中，所选组中的字线与RAS切换。 如果组中包含已知的有缺陷的字线，则该组不被寻址或其选择被禁用。 在每个选定的组中，可以选择一行，交替行或全部行。

公开(公告)号：US5559739A

公开(公告)日：1996-09-24

申请号：US535702

申请日：1995-09-28

申请人： John K. DeBrosse ,  Toshiaki Kirihata ,  Hing Wong

发明人： John K. DeBrosse ,  Toshiaki Kirihata ,  Hing Wong

IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/50 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C29/50 ,  G11C11/401

摘要： A Dynamic Random Access Memory (DRAM) including an array of memory cells arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux input. In this embodiment, the sense amp is connected between the mux's output and the sense amp enable. Because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, the voltage stored in the cells is varied. So, cell signal margin is tested by varying cell signal V.sub.S. V.sub.S may be selected to determine both a high and a low signal margin.

摘要翻译： 一种动态随机存取存储器（DRAM），包括排列成行和列的存储器单元的阵列，每行中的字线响应于行地址，以及每列中的一对互补位线。 DRAM还包括连接在感测使能和该对互补位线之间的每列中的感测放大器。 感测放大器是一对交叉耦合的NFET，其中NFET的源极连接到感测放大器使能。 位线预充电连接到每对互补位线。 位线预充电连接在互补位线对和参考电压之间。 测试控制电路响应于测试控制信号选择性地将感测放大器禁用和位线对保持在预充电状态。 连接在感测放大器和负载使能之间的主动感测放大器负载锁定读出放大器中的数据。 主动感测放大器负载是连接到感测放大器的一对交叉耦合PFET，PFET的源极连接到负载使能。 可选地，每列可以包括多个位线对，每对连接到多路复用器输入。 在本实施例中，感测放大器连接在多路复用器的输出和读出放大器使能之间。 由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。 代替改变感测放大器参考电压，存储在单元中的电压是变化的。 因此，通过改变单元信号VS来测试单元信号余量。 可以选择VS来确定高和低信号余量。

公开(公告)号：US08754412B2

公开(公告)日：2014-06-17

申请号：US13342226

申请日：2012-01-03

申请人： Xiaojun Yu ,  Anda C. Mocuta ,  Toshiaki Kirihata

发明人： Xiaojun Yu ,  Anda C. Mocuta ,  Toshiaki Kirihata

IPC分类号： H01L29/10

CPC分类号： H01L22/34 ,  H01L23/481 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.

摘要翻译： 一种设备，包括通过硅通孔（TSV）连接IDVMON监视器，以使监视器能够连接到位于晶片背面的探针焊盘。 因为晶片的背面具有比前侧大得多的空间，所以可以容纳用于IDVMON的探针垫，而不牺牲硅面积。

公开(公告)号：US08120968B2

公开(公告)日：2012-02-21

申请号：US12704703

申请日：2010-02-12

申请人： William Robert Reohr ,  John Edward Barth, Jr. ,  Toshiaki Kirihata ,  Derek H. Leu ,  Donald W. Plass

发明人： William Robert Reohr ,  John Edward Barth, Jr. ,  Toshiaki Kirihata ,  Derek H. Leu ,  Donald W. Plass

IPC分类号： G11C16/06

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.

摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

公开(公告)号：US20110199837A1

公开(公告)日：2011-08-18

申请号：US12704703

申请日：2010-02-12

申请人： William Robert Reohr ,  John Edward Barth, JR. ,  Toshiaki Kirihata ,  Derek H. Leu ,  Donald W. Plass

发明人： William Robert Reohr ,  John Edward Barth, JR. ,  Toshiaki Kirihata ,  Derek H. Leu ,  Donald W. Plass

IPC分类号： G11C8/08 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.

摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

公开(公告)号：US07885138B2

公开(公告)日：2011-02-08

申请号：US11875173

申请日：2007-10-19

申请人： Hoki Kim ,  Toshiaki Kirihata

发明人： Hoki Kim ,  Toshiaki Kirihata

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18 ,  G11C11/412

摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

摘要翻译： 本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。 存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

公开(公告)号：US20080030260A1

公开(公告)日：2008-02-07

申请号：US11872273

申请日：2007-10-15

申请人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

发明人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

IPC分类号： H01H37/76

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括 所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。

公开(公告)号：US20080025071A1

公开(公告)日：2008-01-31

申请号：US11868046

申请日：2007-10-05

申请人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

发明人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

IPC分类号： G11C11/00

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.

摘要翻译： 用于确定可编程电阻性存储元件的状态的方法包括使第一电平电流通过包括可编程电阻存储器元件的测试电路的熔丝支脚和参考电阻支路; 检测作为第一电流电平的结果，在测试电路的参考节点和熔丝节点之间产生的差分信号; 使第二电流通过保险丝支脚和测试电路的参考支路，第二电平电流高于第一电流电平，以便能够以比与第一电平相比更低的值检测测试电路的跳闸电阻 尊重目前的一级; 以及作为所述第二电流电平的结果，检测在所述参考节点和所述测试电路的所述熔丝节点之间产生的差分信号。