公开(公告)号：US4740926A

公开(公告)日：1988-04-26

申请号：US843356

申请日：1986-03-24

申请人： Yoshihiro Takemae ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Yoshihiro Takemae ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/4091

摘要： A semiconductor memory device comprises a memory cell array, a bit line charge-up circuit coupled to one of a plurality of pairs of bit lines from the memory cell array for initially charging up the one pair of bit lines to a first voltage which is lower than a power source voltage used to drive the semiconductor memory device, an active restore circuit coupled to the one pair of bit lines and a switching circuit coupled to the one pair of bit lines for disconnecting the one pair of bit lines into a first pair of bit line sections on the side of the memory cell array and a second pair of bit line sections on the side of the active restore circuit after the one pair of bit lines are initially charged up to the first voltage. The active restore circuit charges up one of the pair of bit line sections on the side of the active restore circuit to a second voltage which is higher than the first voltage depending on a datum read out from the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，位线充电电路，其耦合到存储单元阵列的多对位线中的一对，用于将一对位线初始充电至较低的第一电压 比用于驱动半导体存储器件的电源电压，耦合到一对位线的有效恢复电路和耦合到该一对位线的开关电路，用于将一对位线断开为第一对位 在存储单元阵列一侧的位线部分和在一对位线开始被充电至第一电压之后的有效恢复电路侧的第二对位线部分。 有源恢复电路根据从存储单元阵列读出的数据，将有源恢复电路一侧的一对位线部分中的一个充电到高于第一电压的第二电压。

公开(公告)号：US4443868A

公开(公告)日：1984-04-17

申请号：US318004

申请日：1981-11-04

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C11/419 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094

摘要： Disclosed is a dynamic-type semiconductor memory device including a group of sense amplifiers, a plurality of pairs of bit lines extending from the sense amplifiers, and a plurality of dynamic-type memory cells connected to each bit line. Each pair of bit lines are short circuited and then precharged to a high potential level before a read operation. According to the present invention, a control line for activating the sense amplifiers is also used as a control line for short circuiting and precharging each pair of bit lines, resulting in a high degree of integration and a high short-circuiting speed.

摘要翻译： 公开了一种动态型半导体存储器件，其包括一组读出放大器，从读出放大器延伸的多对位线以及连接到每个位线的多个动态型存储单元。 每对位线短路，然后在读取操作之前预充电到高电位电平。 根据本发明，用于激活读出放大器的控制线也用作用于短路和预充电每对位线的控制线，导致高集成度和高​​短路速度。

公开(公告)号：US4443720A

公开(公告)日：1984-04-17

申请号：US215630

申请日：1980-12-12

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： H03K5/02 ,  H03K19/017 ,  H03K19/096 ,  H03K5/01

CPC分类号： H03K5/023 ,  H03K19/01735 ,  H03K19/096

摘要： A bootstrap circuit in which a load MOS transistor and a drive MOS transistor are connected in series between a high potential source and a low potential source to form an inverter, a capacitor is connected to an output terminal of the inverter, and a circuit for charging the capacitor and a circuit for discharging the capacitor are connected to the capacitor, the circuit for discharging the capacitor being connected between said capacitor and the low potential source and containing a MOS transistor which is rendered conductive by a reset signal applied to its gate. The present invention involves another MOS transistor having its gate connected to the high potential source being inserted between the MOS transistor in the discharge circuit and the capacitor.

摘要翻译： 一种自举电路，其中负载MOS晶体管和驱动MOS晶体管串联连接在高电位源和低电位源之间以形成逆变器，电容器连接到逆变器的输出端子，并且充电电路 电容器和用于放电电容器的电路连接到电容器，用于将电容器放电的电路连接在所述电容器和低电位源之间，并且包含通过施加到其栅极的复位信号而导通的MOS晶体管。 本发明涉及另一个MOS晶体管，其栅极连接到高电位源，插入放电电路中的MOS晶体管和电容器之间。

公开(公告)号：US4376989A

公开(公告)日：1983-03-15

申请号：US247283

申请日：1981-03-25

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G11C11/407 ,  G11C7/00 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C11/409 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/00

摘要： A semiconductor dynamic memory including a plurality of functional blocks or interface circuits for controlling the memory, such as a row-enable buffer, a row-address buffer, a word decoder, a column-enable buffer, a column-address buffer, and a column decoder. The functional blocks in the semiconductor dynamic memory are sequentially reset by signals from the subsequent functional block so that the power operations of the functional blocks of the subsequent stages is indicated by the reset signal, and thus are returned to the state in which they are ready to execute the next processing.

摘要翻译： 包括用于控制存储器的多个功能块或接口电路的半导体动态存储器，例如行使能缓冲器，行地址缓冲器，字解码器，列使能缓冲器，列地址缓冲器和 列解码器。 半导体动态存储器中的功能块通过来自后续功能块的信号被顺序地复位，使得后续级的功能块的功率操作由复位信号指示，并且因此返回到它们准备好的状态 执行下一个处理。

公开(公告)号：US4267464A

公开(公告)日：1981-05-12

申请号：US968990

申请日：1978-12-13

申请人： Yoshihiro Takemae ,  Masao Nakano

发明人： Yoshihiro Takemae ,  Masao Nakano

IPC分类号： G11C11/41 ,  G11C11/413 ,  H03K5/02 ,  H03K19/096 ,  H03K19/017 ,  G11C8/00

CPC分类号： H03K5/023 ,  H03K19/096

摘要： A decoder circuit including: a charge-up transistor for maintaining the content of an input address signal; a power supply switching transistor for controlling a charge-up current which is supplied to the charge-up transistor; a predetermined number of selection transistors which are connected at a connection point between the charge-up transistor and the power supply switching transistor so as to select an output word line, and; a bootstrap transistor which is connected to an opposite side of the connection point with respect to the charge-up transistor. The present invention enables the driving of the charge-up transistor with clock pulses having a potential level higher than the power supply line voltage V.sub.DD. The present invention also enables the driving of the power supply switching transistor by clock pulses having a potential level higher than V.sub.DD +V.sub.th wherein V.sub.+h equals the threshold voltage of the power supply switching transistor.

摘要翻译： 一种解码器电路，包括：用于维持输入地址信号的内容的充电晶体管; 用于控制提供给所述充电晶体管的充电电流的电源开关晶体管; 预定数量的选择晶体管，其连接在充电晶体管和电源开关晶体管之间的连接点，以选择输出字线; 自举晶体管，其连接到相对于充电晶体管的连接点的相对侧。 本发明使得能够利用具有高于电源线电压VDD的电位电平的时钟脉冲驱动充电晶体管。 本发明还能够通过具有高于VDD + Vth的电位电平的时钟脉冲来驱动电源开关晶体管，其中V + h等于电源开关晶体管的阈值电压。

公开(公告)号：US07937645B2

公开(公告)日：2011-05-03

申请号：US11443109

申请日：2006-05-31

申请人： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

发明人： Toshio Ogawa ,  Yoshihiro Takemae ,  Yoshinori Okajima ,  Tetsuhiko Endo ,  Yasuro Matsuzaki

IPC分类号： G11C29/00

CPC分类号： G11C29/42

摘要： A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.

摘要翻译： 转换控制单元设置对每个控制器启用或禁用的写数据转换单元或读数据转换单元的转换功能。 因此，对于需要原始外部数据的控制器，可以输入和输出外部数据，而对于需要转换的内部数据的控制器，可以输入和输出内部数据。 可以在半导体存储器中实现传统控制器的数据转换功能，这可以减少控制器上的负载。 结果，可以提高系统的性能。 无权访问的无​​效控制器无法读取正确的数据（转换前的原始数据）。 因此，可以保护写入半导体存储器的数据的安全性。

公开(公告)号：US07386659B2

公开(公告)日：2008-06-10

申请号：US11505837

申请日：2006-08-18

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G06F13/38

CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

摘要翻译： 存储器控制器根据要操作的存储器芯片的操作规范，将从控制器输出的控制器输出信号转换为存储器输入信号，并通过公共总线将结果输出到存储器芯片。 存储器控制器还通过公共总线接收从存储器芯片输出的存储器输出信号，并将接收的信号转换成可接收到控制器的控制器输入信号。 这允许单个存储器控制器访问多种类型的存储器芯片。 结果，存储器控制器可以减小芯片尺寸，降低存储器系统的成本。

公开(公告)号：US07370141B2

公开(公告)日：2008-05-06

申请号：US11505838

申请日：2006-08-18

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G06F13/38

CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

公开(公告)号：US20060282608A1

公开(公告)日：2006-12-14

申请号：US11505835

申请日：2006-08-18

申请人： Yoshihiro Takemae

发明人： Yoshihiro Takemae

IPC分类号： G06F12/00

CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0623 ,  G06F13/1694 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072

摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

公开(公告)号：US06737893B2

公开(公告)日：2004-05-18

申请号：US10278076

申请日：2002-10-23

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K522

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.