公开(公告)号：US06707325B2

公开(公告)日：2004-03-16

申请号：US10278080

申请日：2002-10-23

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K300

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

公开(公告)号：US5557221A

公开(公告)日：1996-09-17

申请号：US76434

申请日：1993-06-14

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K19/0185 ,  H03F3/45

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及根据该开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US06737893B2

公开(公告)日：2004-05-18

申请号：US10278076

申请日：2002-10-23

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K522

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

公开(公告)号：US6034555A

公开(公告)日：2000-03-07

申请号：US718045

申请日：1996-09-13

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K19/0185 ,  H03F3/45

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

公开(公告)号：US06744300B2

公开(公告)日：2004-06-01

申请号：US10277707

申请日：2002-10-23

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H01J1982

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US06492846B1

公开(公告)日：2002-12-10

申请号：US09474702

申请日：1999-12-29

申请人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

发明人： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC分类号： H03K300

CPC分类号： H03K19/018585

摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By this constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

摘要翻译： 半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及用于根据所述开关单元的幅度或频率选择性地接通和断开开关单元的控制单元 输入信号。 通过这种结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

公开(公告)号：US5936897A

公开(公告)日：1999-08-10

申请号：US48996

申请日：1998-03-27

申请人： Makoto Koga

发明人： Makoto Koga

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C7/065 ,  G11C7/22

摘要： The present invention relates to a memory device including a sense amplifier for driving bit line pair and write amplifier for driving data bus line connecting to the bit line pair. According to the present invention, when the column gates are opened and the sense amplifiers are connected to the data bus amplifiers via the data bus pair, one sense amplifier circuit portion of each sense amplifier is deactivated and the conflicts which arise from the operation of the write amplifiers in the data bus amplifiers and of the sense amplifiers can be avoided, and the writing operation can be performed at a high speed. In addition, the control of the sense amplifiers need not be changed either for the reading process or for the writing process, and the writing speed can be increased without the reading being affected.

摘要翻译： 本发明涉及包括用于驱动位线对的读出放大器和用于驱动连接到位线对的数据总线的写放大器的存储器件。 根据本发明，当列门打开并且读出放大器经由数据总线对连接到数据总线放大器时，每个读出放大器的一个读出放大器电路部分被去激活，并且由于操作引起的冲突 可以避免数据总线放大器和读出放大器中的写放大器，并且可以高速执行写入操作。 此外，对于读取处理或写入处理，读出放大器的控制不需要改变，并且可以在不影响读取的情况下增加写入速度。

公开(公告)号：US06936889B2

公开(公告)日：2005-08-30

申请号：US10824474

申请日：2004-04-15

申请人： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

发明人： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

IPC分类号： G01R31/28 ,  G11C8/12 ,  G11C29/12 ,  G11C29/26 ,  G11C29/56 ,  G11C5/02

CPC分类号： G11C29/26 ,  G11C8/12

摘要： A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

摘要翻译： 具有至少三个可独立存取存储器的半导体器件，其中至少一个存储器具有与其它存储器不同的存储器容量。 将独立的选择信号提供给存储器，使得它们可以被独立地激活。 这允许记忆分开测试。 当测试半导体器件时，除了具有最大容量的存储器之外，连续测试存储器，因为该存储器也具有最长的测试时间。 具有最长测试时间的存储器与串行测试的存储器并行测试。 这在测试期间将测试装置必须提供的电流减少到半导体器件。

公开(公告)号：US06373414B1

公开(公告)日：2002-04-16

申请号：US09947503

申请日：2001-09-07

申请人： Makoto Koga ,  Yoshinori Okajima

发明人： Makoto Koga ,  Yoshinori Okajima

IPC分类号： H03M900

摘要： According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

公开(公告)号：US06528817B1

公开(公告)日：2003-03-04

申请号：US09626107

申请日：2000-07-26

申请人： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

发明人： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

IPC分类号： H01L2900

CPC分类号： G11C29/26 ,  G11C8/12

摘要： A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

摘要翻译： 具有至少三个可独立存取存储器的半导体器件，其中至少一个存储器具有与其它存储器不同的存储器容量。 将独立的选择信号提供给存储器，使得它们可以被独立地激活。 这允许记忆分开测试。 当测试半导体器件时，除了具有最大容量的存储器之外，连续测试存储器，因为该存储器也具有最长的测试时间。 具有最长测试时间的存储器与串行测试的存储器并行测试。 这在测试期间将测试装置必须提供的电流减少到半导体器件。