公开(公告)号：US4924999A

公开(公告)日：1990-05-15

申请号：US217873

申请日：1988-07-12

Applicant: Shuichi Kikuchi ,  Yoshio Yamamoto ,  Yoshihiko Kawasaki

Inventor： Shuichi Kikuchi ,  Yoshio Yamamoto ,  Yoshihiko Kawasaki

IPC: B65H67/06 ,  B65G25/00

CPC classification number: B65H67/065 ,  B65H2701/31

Abstract: A package transfer system in which packages discharged from a winder in a prostrate posture with the respective longitudinal axis disposed substantially in the horizontal direction are transferred to a next stage and placed with the respective axes in a vertically aligned state. It includes a package aligning device located contiguously to the discharge end of the winder and adapted to align the discharged packages in a stand-by position with the respective axes in the vertical direction and a package transfer device adapted to hang up the packages arbitrarily aligned by the package aligning device for transfer to a next stage in the aligned state.

Abstract translation: 一种包装传送系统，其中以相对于纵向轴线基本上在水平方向上布置的匍匐姿势的络纱机排出的包装被转移到下一个阶段，并且各个轴线以垂直对准的状态放置。 它包括一个连接到卷绕机的排放端的包装对准装置，它适合于将排出的包装物排列在垂直方向上的相应轴线的待机位置，以及包装传送装置，适于将包装任意对齐的包装 该封装对准装置用于在对准状态下传送到下一级。

公开(公告)号：US4688980A

公开(公告)日：1987-08-25

申请号：US821595

申请日：1986-01-23

Applicant: Shuichi Kikuchi ,  Hiroo Otoshima

Inventor： Shuichi Kikuchi ,  Hiroo Otoshima

IPC: B65H67/04 ,  B65H67/06 ,  B65G65/23

CPC classification number: B65H67/06 ,  B65H2701/31

Abstract: A device for feeding spinning bobbins after spinning to a winder comprises a base supporting a bobbin box thereon, a cover member integrally pivoted about a shaft and being positioned in an opening of the bobbin box to prevent a bobbin from falling when the box is inverted, and a driving mechanism for turning the base and the cover member with the bobbin box upside down to transfer the bobbin box onto a bobbin conveyor, and for moving the cover member to a position at least lower than the bobbin carrying surface of the conveyor.

Abstract translation: 用于在旋转到卷绕机之后将纺纱筒管喂入的装置包括：支撑绕线筒的基座;覆盖部件，其一体地绕轴转动并且定位在所述绕线管的开口中，以防止所述线轴在所述箱体倒转时掉落， 以及驱动机构，用于将梭壳的底部和盖部件上下转动以将梭芯传送到筒管传送器上，并且用于将盖部件移动到至少比输送机的筒管承载表面低的位置。

公开(公告)号：US3977171A

公开(公告)日：1976-08-31

申请号：US493508

申请日：1974-08-01

Applicant: Noboru Shindo ,  Hiroshi Hashizume ,  Shuichi Kikuchi

Inventor： Noboru Shindo ,  Hiroshi Hashizume ,  Shuichi Kikuchi

IPC: D02G1/06 ,  D01H7/92 ,  D02G1/04

CPC classification number: D02G1/06

Abstract: A false twisting spindle comprises a turbine including a hollow turbine shaft, a twister pin mounted in the hollow shaft and a turbine blade impeller. The turbine is mounted in a hollow hole of a housing by being supported by means of fluid bearings. The most preferable diameter of the turbine blade impeller is determined depending on the denier of a yarn employed.

公开(公告)号：US08558307B2

公开(公告)日：2013-10-15

申请号：US11958531

申请日：2007-12-18

Applicant: Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shuji Tanaka

Inventor： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shuji Tanaka

IPC: H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835

Abstract: It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and a DMOS transistor is formed in the P+W layer. The epitaxial layer and a drain region are insulated by the P+W layer. Therefore, it is possible to form both the DMOS transistor and other device element in a single confined region surrounded by an isolation layer. An N type FN layer is disposed on the surface region of the P+W layer beneath the gate electrode. An N+D layer, which is adjacent to the edge of the gate electrode of the drain layer side, is also formed. P type impurity layers (a P+D layer and a FP layer), which are located below the drain layer, are disposed beneath the contact region of the drain layer.

Abstract translation: 期望在具有DMOS晶体管的半导体器件中减小芯片面积，降低导通电阻并提高DMOS晶体管的电流驱动能力。 在N型外延层的表面上设置相反导电型（P型）的P + W层，在P + W层形成DMOS晶体管。 外延层和漏极区由P + W层绝缘。 因此，可以在由隔离层包围的单个限制区域内形成DMOS晶体管和其它器件元件。 N型FN层设置在栅电极下面的P + W层的表面区域上。 还形成了与漏极层侧的栅电极的边缘相邻的N + D层。 位于漏极层下方的P型杂质层（P + D层和FP层）设置在漏极层的接触区域的下方。

公开(公告)号：US20110115324A1

公开(公告)日：2011-05-19

申请号：US12926785

申请日：2010-12-09

Applicant: Yuji Shishido ,  Kenichiro Yazawa ,  Shinichiro Kato ,  Shuichi Kikuchi ,  Toru Ujiie

Inventor： Yuji Shishido ,  Kenichiro Yazawa ,  Shinichiro Kato ,  Shuichi Kikuchi ,  Toru Ujiie

IPC: H02K7/08 ,  F16C32/06

CPC classification number: F16C35/02 ,  F16C17/026 ,  F16C17/107 ,  F16C33/103 ,  F16C33/107 ,  F16C41/008 ,  F16C2370/12 ,  G11B19/2018 ,  H02K5/1677 ,  H02K7/085

Abstract: A bearing unit is provided which includes a shaft (51) to support rotatably, radial bearing (55) to support the shaft (51) circumferentially, a thrust bearing (66) to support the shaft (51) in the direction of thrusting, and a housing (56) having the radial bearing (55) and thrust bearing (66) disposed therein and in which a viscous fluid (57) is filled. The housing (56) has a sealed structure except for a shaft insertion hole (65) formed therein and through which the shaft 51 is introduced. Between the outer surface of the shaft (51) and the inner surface of the shaft insertion hole (65), there is defined a gap (69) having a sufficient width to prevent the viscous fluid (57) filled in the housing (56) from leaking out of the latter.

Abstract translation: 提供了一种轴承单元，其包括：轴（51），用于支撑可旋转的径向轴承（55）以沿周向支撑轴（51）;止推轴承（66），以沿轴向方向支撑轴（51）;以及 具有径向轴承（55）的壳体（56）和设置在其中的止推轴承（66），并且其中填充有粘性流体（57）。 壳体56除了形成在其中的轴插入孔65之外还具有密封结构，轴51被引入。 在轴（51）的外表面和轴插入孔（65）的内表面之间限定有足够宽度的间隙（69），以防止填充在壳体（56）中的粘性流体（57） 从后者泄漏出来。

公开(公告)号：US07737523B2

公开(公告)日：2010-06-15

申请号：US11395599

申请日：2006-03-30

Applicant: Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

Inventor： Shuichi Kikuchi ,  Shigeaki Okawa ,  Kiyofumi Nakaya ,  Toshiyuki Takahashi

IPC: H01L29/93

CPC classification number: H01L29/872 ,  H01L29/866

Abstract: In a semiconductor device of the present invention, a protection diode for protecting a device is formed on an epitaxial layer formed on a substrate. A Schottky barrier metal layer is formed on a surface of the epitaxial layer and a P-type diffusion layer is formed at a lower portion of an end portion of the Schottky barrier metal layer. Then, a P-type diffusion layer is formed to be connected to a P-type diffusion layer and is extended to a cathode region. A metal layer to which an anode electrode is applied is formed above the P-type diffusion layer, thereby making it possible to obtain a field plate effect. This structure reduces a large change in a curvature of a depletion layer, thereby improving a withstand voltage characteristic of the protection diode.

Abstract translation: 在本发明的半导体器件中，在形成在基板上的外延层上形成用于保护器件的保护二极管。 在外延层的表面上形成肖特基势垒金属层，在肖特基势垒金属层的端部的下部形成P型扩散层。 然后，形成P型扩散层以连接到P型扩散层并延伸到阴极区。 在P型扩散层的上方形成有施加了阳极电极的金属层，能够得到场板效应。 这种结构减小了耗尽层的曲率的大的变化，从而提高了保护二极管的耐电压特性。

公开(公告)号：US07649224B2

公开(公告)日：2010-01-19

申请号：US11956097

申请日：2007-12-13

Applicant: Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shuji Tanaka

Inventor： Shuichi Kikuchi ,  Kiyofumi Nakaya ,  Shuji Tanaka

IPC: H01L23/62

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404

Abstract: This invention is directed to offer a MOS transistor that has a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer for lowering on resistance in the drift region. The N well layer is disposed beneath the gate electrode and away from the N well layer with a certain space between them. This space ensures the withstand voltage at the edge of the gate electrode of the drain layer side. Also, the N well layer is formed on the surface of an epitaxial layer in the region that includes a P+L layer. The edge of the N well layer of the drain layer side is located near the edge of the P+L layer of the drain layer side and away from the N well layer. This space makes the expansion of depletion layer from the P+L layer easier, further improving the withstand voltage.

Abstract translation: 本发明旨在提供一种具有高的源极 - 漏极击穿BVds，低导通电阻和高电流驱动能力的MOS晶体管。 通过在漂移区域中形成用于降低导通电阻的N阱层来降低电阻。 N阱层设置在栅电极下方并且远离N阱层之间具有一定的间隔。 该空间确保漏极层侧的栅电极的边缘处的耐受电压。 此外，在包括P + L层的区域中，在外延层的表面上形成N阱层。 漏层侧的N阱层的边缘位于漏极层侧的P + L层的边缘附近并远离N阱层。 该空间使得P + L层的耗尽层膨胀更加容易，进一步提高了耐压。

公开(公告)号：US07485922B2

公开(公告)日：2009-02-03

申请号：US11526869

申请日：2006-09-26

Applicant: Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

Inventor： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

IPC: H01L29/06

CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/456 ,  H01L29/7816 ,  H01L29/7833

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.

Abstract translation: 在本发明的半导体器件中，在P型单晶硅基板上形成N型外延层。 衬底和外延层通过隔离区分隔成多个元件形成区域。 每个隔离区域由P型掩埋扩散层和与其耦合的P型扩散层形成。 P型埋入扩散层在其两侧与N型埋入扩散层接合，形成PN结区域。 另一方面，P型扩散层在其两侧与N型扩散层接合，形成PN结区域。 这种结构抑制了P型掩埋扩散层和P型扩散层的宽度方向扩散的扩展，从而可以减小器件尺寸。

公开(公告)号：US07288816B2

公开(公告)日：2007-10-30

申请号：US11360287

申请日：2006-02-22

Applicant: Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake ,  Hirotsugu Hata

Inventor： Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake ,  Hirotsugu Hata

IPC: H01L29/78

CPC classification number: H01L29/7322 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66659 ,  H01L29/735 ,  H01L29/7835

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

公开(公告)号：US20070063274A1

公开(公告)日：2007-03-22

申请号：US11360287

申请日：2006-02-22

Applicant: Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake ,  Hirotsugu Hata

Inventor： Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake ,  Hirotsugu Hata

IPC: H01L29/76

CPC classification number: H01L29/7322 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66659 ,  H01L29/735 ,  H01L29/7835

Abstract: According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.

Abstract translation: 根据本发明的实施例的半导体器件，在衬底和外延层之间形成P型掩埋扩散层。 在P型掩埋扩散层中形成N型埋入扩散层。 在元件形成区域的下方形成过电压保护PN结区域。 PN结区域的击穿电压低于源极 - 漏极击穿电压。 这种结构防止击穿电流集中地流入PN结区域并保护半导体器件免受过电压。