公开(公告)号：US20130075864A1

公开(公告)日：2013-03-28

申请号：US13612194

申请日：2012-09-12

申请人： Seiji OTAKE ,  Yasuhiro TAKEDA ,  Yuta MIYAMOTO

发明人： Seiji OTAKE ,  Yasuhiro TAKEDA ,  Yuta MIYAMOTO

IPC分类号： H01L27/06

CPC分类号： H01L27/0259

摘要： An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.

摘要翻译： ESD保护元件由包括具有适当杂质浓度的N +型掩埋层和P +型掩埋层的PN结二极管和使用连接到P +型扩散层的P +型绘图层的寄生PNP双极晶体管形成，作为 作为基极的N型外延层和作为集电体的P型半导体基板。 P +型埋层与阳极连接，P +型扩散层与P +型扩散层连接并围绕P +型扩散层的N +型扩散层与阴极电极连接。 当向阴极施加大的正静电时，寄生PNP双极晶体管导通以流过大的放电电流。

公开(公告)号：US08022475B2

公开(公告)日：2011-09-20

申请号：US12434128

申请日：2009-05-01

申请人： Yasuhiro Takeda ,  Seiji Otake ,  Kazunori Fujita

发明人： Yasuhiro Takeda ,  Seiji Otake ,  Kazunori Fujita

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/823456 ,  H01L21/2815 ,  H01L21/823412 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7813

摘要： An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer. The trench gate type transistor is formed in the first region of the semiconductor layer and the planar type transistor is formed in the second region of the semiconductor layer.

摘要翻译： 同时优化沟槽栅型晶体管的导通电阻和平面型晶体管的耐电压。 半导体层的第一和第二区域中的每一个分别通过在半导体衬底的第一和第二区域中的每一个上外延生长而形成。 在半导体衬底的第一区域和半导体层的第一区域之间形成第一掩埋层，而在半导体衬底的第二区域和半导体层的第二区域之间形成第二掩埋层。 第一掩埋层由N +型第一杂质掺杂层和延伸超过第一杂质掺杂层的N型第二杂质掺杂层形成。 第二掩埋层仅由N +型杂质掺杂层形成。 在半导体层的第一区域中，杂质从半导体层的表面扩散到半导体层中以形成N型第三杂质掺杂层。 沟槽栅型晶体管形成在半导体层的第一区域中，并且平面型晶体管形成在半导体层的第二区域中。

公开(公告)号：US20070272942A1

公开(公告)日：2007-11-29

申请号：US11751162

申请日：2007-05-21

申请人： Seiji Otake

发明人： Seiji Otake

IPC分类号： H01L29/74

CPC分类号： H01L29/8611 ,  H01L29/7412

摘要： In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, a resistance is formed. Around the resistance, a protection element having a PN junction region is formed. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of the resistance. By use of this structure, when negative ESD surge is applied to a pad for an electrode which applies a voltage to a P type diffusion layer, the PN junction region of the protection element breaks down. Accordingly, the resistance can be protected.

摘要翻译： 在本发明的半导体器件中，N型外延层通过隔离区域分成多个元件形成区域。 在元件形成区域之一中形成电阻。 围绕电阻，形成具有PN结区域的保护元件。 PN结区域的结击穿电压低于电阻的PN结区域的结击穿电压。 通过使用这种结构，当对用于向P型扩散层施加电压的电极的焊盘施加负的静电放电时，保护元件的PN结区域就会发生故障。 因此，可以保护电阻。

公开(公告)号：US07291883B2

公开(公告)日：2007-11-06

申请号：US11360286

申请日：2006-02-22

申请人： Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake

发明人： Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake

IPC分类号： H01L29/792

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66681

摘要： In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.

摘要翻译： 在传统的半导体器件中，存在用于保护元件免于过电压的N型扩散区域窄并且击穿电流被集中以使得用于保护的PN结区域被破坏的问题。 在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。 在N型掩埋扩散层的上表面上的较宽区域上形成P型埋入扩散层，从而形成用于过电压保护的PN结区域。 P型扩散层形成为与P型扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。 利用这种结构，防止了击穿电流的集中，从而可以防止半导体器件免受过电压。

公开(公告)号：US20070148892A1

公开(公告)日：2007-06-28

申请号：US11614527

申请日：2006-12-21

申请人： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

发明人： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

IPC分类号： H01L21/331

CPC分类号： H01L29/735 ,  H01L29/0692 ,  H01L29/6625

摘要： In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, even in a case where the collector region is narrowed, a desired hfe value can be realized. Thus, the device size can be reduced.

摘要翻译： 在本发明的半导体器件中，N型外延层层叠在P型单晶硅基板上。 在外延层中，形成作为基极引出区域的N型扩散层，作为发射极区域的P型扩散层和作为集电极区域的P型扩散层。 发射极区域具有比在其表面附近更深的部分具有较大扩散宽度的区域。 在横向PNP晶体管中，在外延层的深部形成最小的基极宽度。 通过使用该结构，即使在集电极区域变窄的情况下，也能够实现期望的hfe值。 因此，可以减小设备尺寸。

公开(公告)号：US20070145529A1

公开(公告)日：2007-06-28

申请号：US11614496

申请日：2006-12-21

申请人： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

发明人： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

IPC分类号： H01L27/082

CPC分类号： H01L29/735 ,  H01L29/1008 ,  H01L29/6625

摘要： In a semiconductor device of the present invention, an N type epitaxial layer is stacked on a P type single crystal silicon substrate. In the epitaxial layer, an N type diffusion layer as a base draw-out region, P type diffusion layers as an emitter region, and P type diffusion layers as a collector region are formed. The emitter region has a region having a larger diffusion width in a portion deeper than in a vicinity of a surface thereof. In a lateral PNP transistor, a smallest base width is formed in a deep portion of the epitaxial layer. By use of this structure, recombination of free carriers (positive holes) on the surface is prevented. Thus, a desired hfe value can be realized.

摘要翻译： 在本发明的半导体器件中，N型外延层层叠在P型单晶硅基板上。 在外延层中，形成作为基极引出区域的N型扩散层，作为发射极区域的P型扩散层和作为集电极区域的P型扩散层。 发射极区域具有比在其表面附近更深的部分具有较大扩散宽度的区域。 在横向PNP晶体管中，在外延层的深部形成最小的基极宽度。 通过使用这种结构，可以防止表面上游离载体（正孔）的复合。 因此，可以实现期望的hfe值。

公开(公告)号：US20070096261A1

公开(公告)日：2007-05-03

申请号：US11512617

申请日：2006-08-29

申请人： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

发明人： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

IPC分类号： H01L29/861 ,  H01L31/107

CPC分类号： H01L29/866 ,  H01L29/66106

摘要： In a conventional semiconductor device, there is a problem that zener diode characteristics vary due to a crystal defect on a silicon surface, and the like. In a semiconductor device of the present invention, an N type epitaxial layer 4 is formed on a P type single crystal silicon substrate 2. In the epitaxial layer 4, P type diffusion layers 5, 6, 7 and 8 as anode regions and an N type diffusion layer 9 as a cathode region are formed. A PN junction region between the P type diffusion layer 8 and the N type diffusion layer 9 forms a zener diode 1. By use of this structure, a current path is located in a deep portion of the epitaxial layer 4. Thus, it is made possible to prevent a variation in a saturation voltage of the zener diode 1 due to a crystal defect on a surface of the epitaxial layer 4, and the like.

摘要翻译： 在传统的半导体器件中，存在齐纳二极管特性由于硅表面上的晶体缺陷等而变化的问题。 在本发明的半导体器件中，在P型单晶硅基板2上形成有N型外延层4.在外延层4中，作为阳极区域的P型扩散层5,6,7,8，N 形成作为阴极区域的扩散层9。 P型扩散层8和N型扩散层9之间的PN结区域形成齐纳二极管1.通过这种结构，电流路径位于外延层4的深部。因此， 可能防止由于外延层4的表面上的晶体缺陷导致的齐纳二极管1的饱和电压的变化等。

公开(公告)号：US08754479B2

公开(公告)日：2014-06-17

申请号：US13612194

申请日：2012-09-12

申请人： Seiji Otake ,  Yasuhiro Takeda ,  Yuta Miyamoto

发明人： Seiji Otake ,  Yasuhiro Takeda ,  Yuta Miyamoto

IPC分类号： H01L27/06

CPC分类号： H01L27/0259

摘要： An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.

摘要翻译： ESD保护元件由包括具有适当杂质浓度的N +型掩埋层和P +型掩埋层的PN结二极管和使用连接到P +型扩散层的P +型绘图层的寄生PNP双极晶体管形成，作为 作为基极的N型外延层和作为集电体的P型半导体基板。 P +型埋层与阳极连接，P +型扩散层与P +型扩散层连接并围绕P +型扩散层的N +型扩散层与阴极电极连接。 当向阴极施加大的正静电时，寄生PNP双极晶体管导通以流过大的放电电流。

公开(公告)号：US08395210B2

公开(公告)日：2013-03-12

申请号：US12680012

申请日：2008-09-26

申请人： Yasuhiro Takeda ,  Seiji Otake ,  Shuichi Kikuchi

发明人： Yasuhiro Takeda ,  Seiji Otake ,  Shuichi Kikuchi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0696 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/7816

摘要： The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A′. A first body layer 17A′ is formed by this first ion implantation. The first body layer 17A′ is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A′ in the first corner portion 14C1 is higher than that of a conventional transistor.

摘要翻译： 本发明提供了一种DMOS晶体管，其中当通过倾斜离子注入形成体层时，泄漏电流降低，并且处于断开状态的晶体管的源极 - 漏极击穿电压增强。 在形成光致抗蚀剂层18之后，使用光致抗蚀剂层18和栅电极14作为掩模，在栅极电极14的内侧沿箭头A所示的第一方向进行第一离子注入 '。 通过该第一离子注入形成第一体层17A'。 第一主体层17A'形成为从第一角部14C1延伸到栅极14的下方，第一角部14C1中的主体层17A'的P型杂质浓度高于 常规晶体管。

公开(公告)号：US08237241B2

公开(公告)日：2012-08-07

申请号：US12692341

申请日：2010-01-22

申请人： Seiji Otake

发明人： Seiji Otake

IPC分类号： H01L29/86

CPC分类号： H01L27/0259 ,  H01L29/735

摘要： A conventional semiconductor device has a problem that an on-current of a parasitic transistor flows through a surface portion of a semiconductor layer and thus a semiconductor element undergoes thermal breakdown. In a semiconductor device according to the present invention, a protection element is formed with use of an isolation region and N type buried layers. A PN junction region in the protection element is formed on a P type buried layer of the isolation region. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of a semiconductor element to be protected. This structure allows an on-current of a parasitic transistor to flow into the protection element, and thereby the semiconductor element is protected. In addition, the on-current of the parasitic transistor flows through a deep portion of the epitaxial layer, and thereby the protection element is prevented from thermal breakdown.

摘要翻译： 传统的半导体器件具有寄生晶体管的导通电流流过半导体层的表面部分，因此半导体元件经受热击穿的问题。 在根据本发明的半导体器件中，使用隔离区域和N型掩埋层形成保护元件。 保护元件中的PN结区域形成在隔离区域的P型掩埋层上。 PN结区域的结击穿电压低于要保护的半导体元件的PN结区域的结击穿电压。 这种结构允许寄生晶体管的导通电流流入保护元件，从而保护半导体元件。 此外，寄生晶体管的导通电流流过外延层的深部，由此防止了保护元件的热击穿。