公开(公告)号：US20100204885A1

公开(公告)日：2010-08-12

申请号：US12670478

申请日：2008-11-21

申请人： Hideonori Kajino ,  Ryo Kanda

发明人： Hideonori Kajino ,  Ryo Kanda

IPC分类号： G06F19/00

CPC分类号： B60G17/0157 ,  B60G17/0165 ,  B60G17/018 ,  B60G17/025 ,  B60G21/0555 ,  B60G2200/184 ,  B60G2202/134 ,  B60G2202/42 ,  B60G2400/102 ,  B60G2400/206 ,  B60G2400/208 ,  B60G2400/252 ,  B60G2400/821 ,  B60G2400/91 ,  B60G2400/954 ,  B60G2500/30 ,  B60G2600/182 ,  B60G2600/60 ,  B60G2800/162

摘要： A suspension system including: (a) a vibration obtaining device configured to obtain vertical vibration of each of at least one of a sprung portion and an unsprung portion of a vehicle; (b) a processing device configured to subject the obtained vibration to a phase advance processing, and having a plurality of characteristics different from each other with respect to a degree by which a phase of the obtained vibration is advanced; (c) a characteristic selector configured to select one of the plurality of characteristics, based on frequency of the obtained vibration of each of at least one of the sprung and unsprung portions, whereby the obtained vibration is subjected to the phase advance processing that is performed in accordance with the selected one of the plurality of characteristics of the processing device; and (d) a suspension controller configured to control a suspension disposed between the sprung and unsprung portions, based on the vibration subjected to the phase advance processing.

摘要翻译： 一种悬架系统，包括：（a）振动获取装置，被配置为获得车辆的弹簧部分和簧下部分中的至少一个的垂直振动; （b）处理装置，被配置为使所获得的振动进行相位提前处理，并且具有相对于获得的振动的相位提前的程度彼此不同的多个特性; （c）特征选择器，其被配置为基于所获得的振动中的至少一个的簧上和簧下部分的振动的频率来选择所述多个特性中的一个，由此所获得的振动经受执行的相位超前处理 根据处理装置的多个特征中选择的一个; 以及（d）悬架控制器，被配置为基于经过相位超前处理的振动来控制设置在簧上和簧下部分之间的悬架。

公开(公告)号：US07741694B2

公开(公告)日：2010-06-22

申请号：US10950611

申请日：2004-09-27

申请人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

发明人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC分类号： H01L29/00

CPC分类号： H01L21/8224 ,  H01L27/0821 ,  H01L29/7322

摘要： A semiconductor integrated circuit device according to the present invention includes an N-type embedded diffusion region between a substrate and an epitaxial layer in first and second island regions serving as small signal section. The N-type embedded diffusion region connects to N-type diffusion regions having supply potential. The substrate and the epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

摘要翻译： 根据本发明的半导体集成电路器件包括用作小信号部分的第一和第二岛区中的衬底和外延层之间的N型嵌入扩散区域。 N型嵌入扩散区域连接到具有电源电位的N型扩散区域。 因此，衬底和外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入式扩散区域分隔开。 这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。

公开(公告)号：US07732880B2

公开(公告)日：2010-06-08

申请号：US11770306

申请日：2007-06-28

申请人： Ryo Kanda ,  Iwao Takahashi ,  Yoshinori Sato

发明人： Ryo Kanda ,  Iwao Takahashi ,  Yoshinori Sato

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66681

摘要： A conventional semiconductor device, for example, a MOS transistor including an offset gate structure has a problem that it is difficult to reduce the device size. In a semiconductor device according to the present invention, for example, in a P-channel MOS transistor including an offset gate structure, a LOCOS oxide film is formed between a source region and a drain region in an N type epitaxial layer. A gate electrode is formed to be positioned on the LOCOS oxide layer. In addition, a P type diffusion layer as the drain region and a P type diffusion layer as the source region are formed with a high positional accuracy with respect to the gate electrode. This structure makes it possible to reduce the device size of the MOS transistor.

摘要翻译： 常规的半导体器件，例如包括偏移栅极结构的MOS晶体管具有难以减小器件尺寸的问题。 在根据本发明的半导体器件中，例如，在包括偏移栅极结构的P沟道MOS晶体管中，在N型外延层中的源极区域和漏极区域之间形成LOCOS氧化物膜。 栅电极被形成为位于LOCOS氧化物层上。 此外，作为漏极区域的P型扩散层和作为源极区域的P型扩散层以相对于栅电极的高位置精度形成。 这种结构使得可以减小MOS晶体管的器件尺寸。

公开(公告)号：US20080001238A1

公开(公告)日：2008-01-03

申请号：US11770306

申请日：2007-06-28

申请人： Ryo Kanda ,  Iwao Takahashi ,  Yoshinori Sato

发明人： Ryo Kanda ,  Iwao Takahashi ,  Yoshinori Sato

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66681

摘要： A conventional semiconductor device, for example, a MOS transistor including an offset gate structure has a problem that it is difficult to reduce the device size. In a semiconductor device according to the present invention, for example, in a P-channel MOS transistor including an offset gate structure, a LOCOS oxide film is formed between a source region and a drain region in an N type epitaxial layer. A gate electrode is formed to be positioned on the LOCOS oxide layer. In addition, a P type diffusion layer as the drain region and a P type diffusion layer as the source region are formed with a high positional accuracy with respect to the gate electrode. This structure makes it possible to reduce the device size of the MOS transistor.

摘要翻译： 常规的半导体器件，例如包括偏移栅极结构的MOS晶体管具有难以减小器件尺寸的问题。 在根据本发明的半导体器件中，例如，在包括偏移栅极结构的P沟道MOS晶体管中，在N型外延层中的源极区域和漏极区域之间形成LOCOS氧化物膜。 栅电极被形成为位于LOCOS氧化物层上。 此外，作为漏极区域的P型扩散层和作为源极区域的P型扩散层以相对于栅电极的高位置精度形成。 这种结构使得可以减小MOS晶体管的器件尺寸。

公开(公告)号：US07279768B2

公开(公告)日：2007-10-09

申请号：US11361173

申请日：2006-02-23

申请人： Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake

发明人： Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake

IPC分类号： H01L23/58

CPC分类号： H01L29/7835 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7816

摘要： In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.

摘要翻译： 在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。 在宽范围内在N型掩埋扩散层的上表面上形成P型掩埋扩散层，以形成用于过电压保护的PN结区域。 P型扩散区形成为与P型埋入扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。 这种结构使得可以防止击穿电流的集中并且保护半导体器件免于过电压。

公开(公告)号：US20070075363A1

公开(公告)日：2007-04-05

申请号：US11526869

申请日：2006-09-26

申请人： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

发明人： Seiji Otake ,  Ryo Kanda ,  Shuichi Kikuchi

IPC分类号： H01L29/76

CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/456 ,  H01L29/7816 ,  H01L29/7833

摘要： In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.

摘要翻译： 在本发明的半导体器件中，在P型单晶硅基板上形成N型外延层。 衬底和外延层通过隔离区分隔成多个元件形成区域。 每个隔离区域由P型掩埋扩散层和与其耦合的P型扩散层形成。 P型埋入扩散层在其两侧与N型埋入扩散层接合，形成PN结区域。 另一方面，P型扩散层在其两侧与N型扩散层接合，形成PN结区域。 这种结构抑制了P型掩埋扩散层和P型扩散层的宽度方向扩散的扩展，从而可以减小器件尺寸。

公开(公告)号：US20060186507A1

公开(公告)日：2006-08-24

申请号：US11361173

申请日：2006-02-23

申请人： Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake

发明人： Ryo Kanda ,  Shuichi Kikuchi ,  Seiji Otake

IPC分类号： H01L23/58

CPC分类号： H01L29/7835 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7816

摘要： In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across an upper surface of the N-type buried diffusion layer over a wide range to form a PN junction region for an overvoltage protection. A P-type diffusion region is formed so as to be connected to the P-type buried diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. This structure makes it possible to prevent a concentration of a breakdown current and protect the semiconductor device from an overvoltage.

摘要翻译： 在本发明的半导体器件中，在衬底和外延层上形成N型掩埋扩散层。 在宽范围内在N型掩埋扩散层的上表面上形成P型掩埋扩散层，以形成用于过电压保护的PN结区域。 P型扩散区形成为与P型埋入扩散层连接。 PN结区域的击穿电压低于源极和漏极之间的击穿电压。 这种结构使得可以防止击穿电流的集中并且保护半导体器件免于过电压。

公开(公告)号：US20050077571A1

公开(公告)日：2005-04-14

申请号：US10950610

申请日：2004-09-27

申请人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

发明人： Ryo Kanda ,  Shigeaki Okawa ,  Kazuhiro Yoshitake

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8224 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L31/113

CPC分类号： H01L27/0826 ,  H01L21/8224 ,  H01L27/0821

摘要： A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus partitioned by the N-type embedded diffusion region having supply potential in the island regions serving as small signal section. This structure prevents the inflow of free carriers (electrons) generated from a power NPN transistor due to the back electromotive force of the motor into the small signal section, thus preventing the malfunction of the small signal section.

摘要翻译： 根据本发明的半导体集成电路器件包括在用作小信号部分的岛区中的衬底和第一外延层之间的N型嵌入扩散区域。 因此，衬底和第一外延层被用作小信号部分的岛区域中具有电源电位的N型嵌入扩散区域分隔开。 这种结构防止由于电动机的反电动势进入小信号部分而从电力NPN晶体管产生的自由载流子（电子）的流入，从而防止小信号部分的故障。

公开(公告)号：US08265825B2

公开(公告)日：2012-09-11

申请号：US12670478

申请日：2008-11-21

申请人： Hideonori Kajino ,  Ryo Kanda

发明人： Hideonori Kajino ,  Ryo Kanda

IPC分类号： B60G17/00

CPC分类号： B60G17/0157 ,  B60G17/0165 ,  B60G17/018 ,  B60G17/025 ,  B60G21/0555 ,  B60G2200/184 ,  B60G2202/134 ,  B60G2202/42 ,  B60G2400/102 ,  B60G2400/206 ,  B60G2400/208 ,  B60G2400/252 ,  B60G2400/821 ,  B60G2400/91 ,  B60G2400/954 ,  B60G2500/30 ,  B60G2600/182 ,  B60G2600/60 ,  B60G2800/162

摘要： A suspension system including: (a) a vibration obtaining device configured to obtain vertical vibration of each of at least one of a sprung portion and an unsprung portion of a vehicle; (b) a processing device configured to subject the obtained vibration to a phase advance processing, and having a plurality of characteristics different from each other with respect to a degree by which a phase of the obtained vibration is advanced; (c) a characteristic selector configured to select one of the plurality of characteristics, based on frequency of the obtained vibration of each of at least one of the sprung and unsprung portions, whereby the obtained vibration is subjected to the phase advance processing that is performed in accordance with the selected one of the plurality of characteristics of the processing device; and (d) a suspension controller configured to control a suspension disposed between the sprung and unsprung portions, based on the vibration subjected to the phase advance processing.

摘要翻译： 一种悬架系统，包括：（a）振动获取装置，被配置为获得车辆的弹簧部分和簧下部分中的至少一个的垂直振动; （b）处理装置，被配置为使所获得的振动进行相位提前处理，并且具有相对于获得的振动的相位提前的程度彼此不同的多个特性; （c）特征选择器，其被配置为基于所获得的振动中的至少一个的簧上和簧下部分的振动的频率来选择所述多个特性中的一个，由此所获得的振动经受执行的相位超前处理 根据处理装置的多个特征中选择的一个; 以及（d）悬架控制器，被配置为基于经过相位超前处理的振动来控制设置在簧上和簧下部分之间的悬架。

公开(公告)号：US07547950B2

公开(公告)日：2009-06-16

申请号：US11770238

申请日：2007-06-28

申请人： Ryo Kanda ,  Iwao Takahashi ,  Yoshinori Sato

发明人： Ryo Kanda ,  Iwao Takahashi ,  Yoshinori Sato

IPC分类号： H01L27/088

CPC分类号： H01L29/7816 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681

摘要： A conventional semiconductor device has a problem that it is difficult to obtain a desired breakdown voltage characteristic due to a reduction in a punch-through breakdown voltage between drain and source regions. In a semiconductor device according to the present invention, a P type diffusion layer is formed in an N type epitaxial layer. An N type diffusion layer as a back gate region is formed in the P type diffusion layer. The N type diffusion layer is formed by self-alignment using a drain electrode. This structure makes it possible to increase an impurity concentration of the N type diffusion layer in a vicinity of a P type diffusion layer as a source region. As a result, it is possible to improve a punch-through breakdown voltage between the drain and the source regions, and to achieve a desired breakdown voltage characteristic of the MOS transistor.

摘要翻译： 常规的半导体器件具有由于漏极和源极区域之间的穿通击穿电压降低而难以获得期望的击穿电压特性的问题。 在根据本发明的半导体器件中，在N型外延层中形成P型扩散层。 在P型扩散层中形成作为背栅区的N型扩散层。 通过使用漏电极的自对准形成N型扩散层。 该结构使得可以增加作为源极区域的P型扩散层附近的N型扩散层的杂质浓度。 结果，可以提高漏极和源极区域之间的穿通击穿电压，并且实现MOS晶体管的期望的击穿电压特性。