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    Modular memory device
    63.
    发明授权
    Modular memory device 有权
    模块化存储设备

    公开(公告)号：US06545891B1

    公开(公告)日：2003-04-08

    申请号：US09638334

    申请日：2000-08-14

    申请人： J. James Tringali ,  P. Michael Farmwald ,  Thomas H. Lee ,  Mark G. Johnson ,  Derek J. Bosch

    发明人： J. James Tringali ,  P. Michael Farmwald ,  Thomas H. Lee ,  Mark G. Johnson ,  Derek J. Bosch

    IPC分类号： G11C502

    CPC分类号： G11C5/025 ,  G11C5/063

    摘要： A modular memory device includes a support element, a memory unit comprising a three-dimensional memory array carried by the support element, a device interface unit carried by the support element and coupled with the memory unit, and an electrical connector carried by the support element and coupled with the device interface unit. The memory array is well suited for use as a digital medium storage device for digital media such as digital text, digital music, digital image or images, and digital video. The device interface unit is not required in all cases.

    摘要翻译： 模块化存储器件包括支撑元件，包括由支撑元件承载的三维存储器阵列的存储器单元，由支撑元件承载并与存储器单元耦合的器件接口单元，以及由支撑元件承载的电连接器 并与设备接口单元耦合。 存储器阵列非常适合用作数字媒体的数字媒体存储设备，例如数字文本，数字音乐，数字图像或图像以及数字视频。 在所有情况下都不需要设备接口单元。

    Low cost three-dimensional memory array
    64.
    发明授权
    Low cost three-dimensional memory array 有权
    低成本三维存储阵列

    公开(公告)号：US06515888B2

    公开(公告)日：2003-02-04

    申请号：US09928969

    申请日：2001-08-13

    申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  N. Johan Knall

    发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  P. Michael Farmwald ,  N. Johan Knall

    IPC分类号： G11C1100

    CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L27/0688

    摘要： A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

    摘要翻译： 低成本存储单元阵列包括多个垂直堆叠的存储单元层。 在一种形式中，每个存储单元的特征在于小的横截面积和小于6.3微安培的读取电流。 所得到的存储器阵列具有缓慢的访问时间，并且非常适合于数字媒体存储，其中访问时间要求低，并且与所公开的存储器阵列相关联的显着的成本降低特别有吸引力。 在另一种形式中，每个存储器单元包括反熔丝层和二极管部件，其中至少一个二极管部件被重掺杂（掺杂浓度大于1019 / cm3），并且其中读取电流大（高达500mA）。

    Integrated circuit structure including three-dimensional memory array
    65.
    发明授权
    Integrated circuit structure including three-dimensional memory array 有权
    集成电路结构包括三维存储阵列

    公开(公告)号：US06385074B1

    公开(公告)日：2002-05-07

    申请号：US09748816

    申请日：2000-12-22

    申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

    发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

    IPC分类号： G11C1700

    CPC分类号： H01L27/1021 ,  G11C11/5692 ,  G11C17/14 ,  G11C17/16 ,  G11C2213/71 ,  H01L27/0203 ,  H01L27/115

    摘要： An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

    摘要翻译： 集成电路器件包括三维存储器阵列和阵列端子电路，用于向阵列的选定存储单元提供不同于读取电压的写入电压。 两个电压都不一定等于提供给集成电路的VDD电源电压。 特别是如果大于VDD的写入电压可以由片上电压发生器（例如电荷泵）产生，其可能需要不期望的大量管芯面积，特别是相对于较高位密度的三维存储器阵列 完全以半导体衬底上的层形成。 在几个优选实施例中，存储器阵列正下方的区域有利地用于布置写入电压发生器中的至少一些，从而在写入操作期间将发生器定位在选定的存储器单元附近。

    Differential comparator for amplifying small swing signals to a full swing output
    67.
    再颁专利
    Differential comparator for amplifying small swing signals to a full swing output 失效
    用于将小摆动信号放大到全摆幅输出的差分比较器

    公开(公告)号：USRE36781E

    公开(公告)日：2000-07-18

    申请号：US291091

    申请日：1999-04-13

    申请人： Thomas H. Lee ,  Kevin S. Donnelly

    发明人： Thomas H. Lee ,  Kevin S. Donnelly

    IPC分类号： H03F3/72 ,  H03K3/356 ,  H03K5/24 ,  H03K17/10 ,  H03F3/45 ,  H03K17/04

    CPC分类号： H03K5/249 ,  H03F3/72 ,  H03K3/356121 ,  H03K5/2481

    摘要： A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.

    摘要翻译： 将小摆幅信号放大到全摆幅信号的差分比较器。 差分比较器包括电流开关，其具有耦合以接收一对小摆动互补输入信号的一对输入和输出互补信号的一对互补输出。 由电流开关输出的互补信号具有响应于互补输入信号而围绕预定电压中心的电压摆幅。 差分比较器还包括耦合以接收输出互补信号的第一和第二反相器，其中每个反相器具有对应于预定电压的跳变点电压[相等]。 第一和第二反相器响应于电流开关输出的互补信号输出全摆幅互补输出信号。