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公开(公告)号：US06545891B1
公开(公告)日：2003-04-08
申请号：US09638334
申请日：2000-08-14
IPC分类号： G11C502
摘要： A modular memory device includes a support element, a memory unit comprising a three-dimensional memory array carried by the support element, a device interface unit carried by the support element and coupled with the memory unit, and an electrical connector carried by the support element and coupled with the device interface unit. The memory array is well suited for use as a digital medium storage device for digital media such as digital text, digital music, digital image or images, and digital video. The device interface unit is not required in all cases.
摘要翻译： 模块化存储器件包括支撑元件，包括由支撑元件承载的三维存储器阵列的存储器单元，由支撑元件承载并与存储器单元耦合的器件接口单元，以及由支撑元件承载的电连接器 并与设备接口单元耦合。 存储器阵列非常适合用作数字媒体的数字媒体存储设备，例如数字文本，数字音乐，数字图像或图像以及数字视频。 在所有情况下都不需要设备接口单元。
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公开(公告)号：US06867992B2
公开(公告)日：2005-03-15
申请号：US10342122
申请日：2003-01-13
IPC分类号： G06K19/077 , G11C5/00 , G11C5/02 , G11C5/06
摘要： In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.
摘要翻译： 在一个实施例中，呈现模块化存储器件，其包括衬底，在衬底上方制造的存储器阵列，以及在衬底上和存储器阵列下方制造的第一和第二电路。 第一和第二电路允许模块化存储器件分别与第一和第二种类型的主机设备接口。 在另一个实施例中，提出了一种模块化存储器件，其包括衬底，在衬底上方制造的存储器阵列，在衬底上制造的存储器阵列支持电路，以及在衬底上以及在存储器阵列之下的逻辑电路。
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公开(公告)号：US06515888B2
公开(公告)日：2003-02-04
申请号：US09928969
申请日：2001-08-13
IPC分类号： G11C1100
CPC分类号： H01L27/101 , G11C17/16 , H01L27/0688
摘要： A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).
摘要翻译： 低成本存储单元阵列包括多个垂直堆叠的存储单元层。 在一种形式中，每个存储单元的特征在于小的横截面积和小于6.3微安培的读取电流。 所得到的存储器阵列具有缓慢的访问时间，并且非常适合于数字媒体存储，其中访问时间要求低，并且与所公开的存储器阵列相关联的显着的成本降低特别有吸引力。 在另一种形式中，每个存储器单元包括反熔丝层和二极管部件，其中至少一个二极管部件被重掺杂（掺杂浓度大于1019 / cm3），并且其中读取电流大（高达500mA）。
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4.发明授权Vertically stacked field programmable nonvolatile memory and method of fabrication 有权垂直堆叠现场可编程非易失性存储器和制造方法公开(公告)号：US06351406B1
公开(公告)日：2002-02-26
申请号：US09714440
申请日：2000-11-15
IPC分类号： G11C1700
CPC分类号： G11C17/14 , G11C11/5692 , G11C13/003 , G11C2213/71 , G11C2213/76
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译： 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。
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5.发明授权Vertically stacked field programmable nonvolatile memory and method of fabrication 有权垂直堆叠现场可编程非易失性存储器和制造方法公开(公告)号：US06185122B2
公开(公告)日：2001-02-06
申请号：US09469658
申请日：1999-12-22
IPC分类号： G11C1700
CPC分类号： H01L27/1021 , G11C11/5678 , G11C11/5692 , G11C13/003 , G11C17/16 , G11C2213/71 , G11C2213/76
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译： 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。
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公开(公告)号：US20110156044A1
公开(公告)日：2011-06-30
申请号：US13027113
申请日：2011-02-14
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译： 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。
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公开(公告)号：US07308065B2
公开(公告)日：2007-12-11
申请号：US11406557
申请日：2006-04-18
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
摘要翻译： 适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。 第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟 从所述多个相位矢量中选择并具有第二参考时钟。
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公开(公告)号：US07129538B2
公开(公告)日：2006-10-31
申请号：US10842008
申请日：2004-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
IPC分类号： H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
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9.发明授权公开(公告)号：US07978492B2
公开(公告)日：2011-07-12
申请号：US12725269
申请日：2010-03-16
申请人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
IPC分类号： G11C5/06
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译： 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。
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10.发明申请公开(公告)号：US20100171152A1
公开(公告)日：2010-07-08
申请号：US12725269
申请日：2010-03-16
申请人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , James M. Cleeves
IPC分类号： H01L27/10
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译： 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。
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