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    Phase detector with minimized phase detection error
    2.
    发明授权
    Phase detector with minimized phase detection error 失效

    公开(公告)号：US06642746B2

    公开(公告)日：2003-11-04

    申请号：US10247878

    申请日：2002-09-20

    申请人： Kevin S. Donnelly ,  Thomas H. Lee ,  Tsyr-Chyang Ho

    发明人： Kevin S. Donnelly ,  Thomas H. Lee ,  Tsyr-Chyang Ho

    IPC分类号： H03K526

    CPC分类号： H03D13/008

    摘要： A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.

    Phase detector with minimized phase detection error
    3.
    发明授权
    Phase detector with minimized phase detection error 有权
    相位检测器，具有最小的相位检测误差

    公开(公告)号：US06480035B1

    公开(公告)日：2002-11-12

    申请号：US09707491

    申请日：2000-11-06

    申请人： Kevin S. Donnelly ,  Thomas H. Lee ,  Tsyr-Chyang Ho

    发明人： Kevin S. Donnelly ,  Thomas H. Lee ,  Tsyr-Chyang Ho

    IPC分类号： H03K526

    CPC分类号： G01R25/00 ,  H03L7/085

    摘要： A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.

    摘要翻译： 描述了一种相位检测器，其包括呈现高差分阻抗和低共模阻抗的负载电路。 负载电路耦合到（1）电源和（2）第一节点和第二节点。 第一和第二节点形成相位检测器的输出。 电容电路具有（1）耦合到第一节点和地的第一电容器和（2）耦合到第二节点和地的第二电容器。 第一电路耦合到第一和第二节点，用于检测第一信号和第二信号之间的相位差。 第二电路耦合到第一和第二节点，用于检测第一和第二信号之间的相位差，并且用于使第一电路的相位检测误差最小化，使得能够以最小相位检测来检测第一和第二信号之间的相位差 错误。 第一和第二电路中的每一个接收第一和第二信号和参考信号。 第二电路交叉耦合到第一电路，使得由第二电路产生的误差电流消除由第一电路产生的误差电流，使得相位检测器以最小的相位检测误差检测第一和第二信号之间的相位差。

    Amplifier with active duty cycle correction
    4.
    发明授权
    Amplifier with active duty cycle correction 失效
    具有有效占空比校正功能的放大器

    公开(公告)号：US5572158A

    公开(公告)日：1996-11-05

    申请号：US548900

    申请日：1995-09-18

    申请人： Thomas H. Lee ,  Kevin S. Donnelly ,  Tsyr-Chyang Ho

    发明人： Thomas H. Lee ,  Kevin S. Donnelly ,  Tsyr-Chyang Ho

    IPC分类号： H03K5/08 ,  H03K3/017

    CPC分类号： H03K5/086

    摘要： A circuit is provided which actively corrects the duty cycle of a periodic signal such as a clock signal. The amplifier circuit includes a duty cycle error measurement circuit which measures the error of the output signal from a predetermined duty cycle, for example, 50% duty cycle. A correcting signal is generated from the error signal output by the duty cycle error measurement circuit. The correcting signal is combined with the uncorrected input signal to the circuit to function to offset the signal in order to correct the duty cycle, the combined signals are input to an integrating capacitance to generate a slew limited signal. By varying the amount of the correcting signal and therefore the symmetry of the slew limited signal, the duty cycle of the output can be varied to generate a signal with the desired duty cycle.

    摘要翻译： 提供一种电路，其主动地校正诸如时钟信号的周期性信号的占空比。 放大器电路包括占空比误差测量电路，其测量来自预定占空比的输出信号的误差，例如50％占空比。 由占空比误差测量电路输出的误差信号产生校正信号。 校正信号与未校正的输入信号组合到电路以用于偏移信号以便校正占空比，组合信号被输入到积分电容以产生转换限制信号。 通过改变校正信号的量并因此改变转换限制信号的对称性，可以改变输出的占空比以产生具有所需占空比的信号。

    Delay-locked loop
    5.
    发明授权
    Delay-locked loop 失效
    延迟锁定环路

    公开(公告)号：US5614855A

    公开(公告)日：1997-03-25

    申请号：US512597

    申请日：1995-08-21

    申请人： Thomas H. Lee ,  Kevin S. Donnelly ,  Tsyr-Chyang Ho ,  Mark G. Johnson

    发明人： Thomas H. Lee ,  Kevin S. Donnelly ,  Tsyr-Chyang Ho ,  Mark G. Johnson

    IPC分类号： G01R31/28 ,  H03L7/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/093 ,  H03K5/13

    CPC分类号： H03L7/0812

    摘要： A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. For example, when a data receiver is used as the phase detector in the DLL, the output of the DLL is a clock signal which can be used as a sampling clock for data receivers elsewhere in the system, and is timed to sample data at the optional instant independent of temperature, supply voltage and process variations. Alternatively, a quadrature phase detector may be employed to generate a clock signal that possesses a quadrature (90.degree. ) relationship with a reference clock signal input. This may be used, for example, to generate a transmit clock for a data transmission device. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. Additionally, the inputs to the charge pump are reversed in alternate quadrants of the phase plane in order to enable unlimited phase shift with a finite control voltage range.

    摘要翻译： 描述了延迟锁定环（DLL），其中相位检测器将DLL的输出的相位与参考输入的相位进行比较。 相位比较器的输出驱动一个差分电荷泵，用于对相位比较器输出信号随时间进行积分。 电荷泵输出控制无限幅度的移相器，可调节DLL输出的相位，使相位比较器的输出平均高达50％的时间。 因为DLL调整移相器，直到相位检测器的输出高达50％的时间，平均而言，DLL输出时钟与输入参考时钟的关系仅取决于所使用的相位检测器的类型。 例如，当数据接收器用作DLL中的相位检测器时，DLL的输出是可以用作系统中其他地方的数据接收器的采样时钟的时钟信号，并且被定时以在 可选速度独立于温度，电源电压和工艺变化。 或者，可以采用正交相位检测器来产生与参考时钟信号输入具有正交（90°）关系的时钟信号。 这可以用于例如为数据传输设备产生传输时钟。 此外，DLL被控制以最小化抖动抖动，同时最小化采集时间。 此外，采用占空比校正放大器来产生具有期望占空比的DLL输出时钟，例如50％。 此外，电荷泵的输入在相平面的交替象限中反转，以便在有限的控制电压范围内实现无限相移。

    Delay locked loop circuitry for clock delay adjustment
    6.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 失效
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US07039147B2

    公开(公告)日：2006-05-02

    申请号：US10366865

    申请日：2003-02-14

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H03D3/24

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。

    Differential comparator for amplifying small swing signals to a full swing output
    7.
    再颁专利
    Differential comparator for amplifying small swing signals to a full swing output 失效
    用于将小摆动信号放大到全摆幅输出的差分比较器

    公开(公告)号：USRE36781E

    公开(公告)日：2000-07-18

    申请号：US291091

    申请日：1999-04-13

    申请人： Thomas H. Lee ,  Kevin S. Donnelly

    发明人： Thomas H. Lee ,  Kevin S. Donnelly

    IPC分类号： H03F3/72 ,  H03K3/356 ,  H03K5/24 ,  H03K17/10 ,  H03F3/45 ,  H03K17/04

    CPC分类号： H03K5/249 ,  H03F3/72 ,  H03K3/356121 ,  H03K5/2481

    摘要： A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.

    摘要翻译： 将小摆幅信号放大到全摆幅信号的差分比较器。 差分比较器包括电流开关，其具有耦合以接收一对小摆动互补输入信号的一对输入和输出互补信号的一对互补输出。 由电流开关输出的互补信号具有响应于互补输入信号而围绕预定电压中心的电压摆幅。 差分比较器还包括耦合以接收输出互补信号的第一和第二反相器，其中每个反相器具有对应于预定电压的跳变点电压[相等]。 第一和第二反相器响应于电流开关输出的互补信号输出全摆幅互补输出信号。

    Delay locked loop circuitry for clock delay adjustment
    8.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 有权
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US06539072B1

    公开(公告)日：2003-03-25

    申请号：US09524402

    申请日：2000-03-13

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H04L700

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Low pass filter for a delay locked loop circuit
    9.
    发明授权
    Low pass filter for a delay locked loop circuit 失效
    用于延迟锁定环路的低通滤波器

    公开(公告)号：US06369626B1

    公开(公告)日：2002-04-09

    申请号：US08966721

    申请日：1997-11-10

    申请人： Kevin S. Donnelly ,  Andy Chan ,  Thomas H. Lee ,  Wayne Richardson ,  Jared L. Zerbe ,  Chaofeng Huang ,  Clemenz L. Portmann ,  Grace Tsang

    发明人： Kevin S. Donnelly ,  Andy Chan ,  Thomas H. Lee ,  Wayne Richardson ,  Jared L. Zerbe ,  Chaofeng Huang ,  Clemenz L. Portmann ,  Grace Tsang

    IPC分类号： H03L300

    CPC分类号： H03K5/1565 ,  H03L7/0896 ,  H03L7/093

    摘要： A low pass filter having a first mode of operation and a second mode of operation. The low pass filter includes a charging circuit, a capacitor circuit, and low power circuitry coupled to the capacitor circuit and the charging circuit. The capacitor circuit stores a first differential voltage when the low pass filter is operating in the first mode of operation. The capacitor circuit stores a second differential voltage when the low pass filter is operating in the second mode of operation. The second differential voltage is substantially equal to the first differential voltage. The charging circuit may include a charging current source coupled to a current steering circuit. The low pass filter may further include a load circuit coupled to the current steering circuit and the low power circuitry. The low pass filter may be used in a delay locked loop circuit or a phase locked loop circuit.

    摘要翻译： 具有第一操作模式和第二操作模式的低通滤波器。 低通滤波器包括充电电路，电容器电路和耦合到电容器电路和充电电路的低功率电路。 当低通滤波器在第一操作模式下操作时，电容器电路存储第一差分电压。 当低通滤波器在第二操作模式下工作时，电容器电路存储第二差分电压。 第二差分电压基本上等于第一差分电压。 充电电路可以包括耦合到电流转向电路的充电电流源。 低通滤波器还可以包括耦合到电流转向电路和低功率电路的负载电路。 低通滤波器可用于延迟锁定环电路或锁相环电路中。

    Phase detector with minimized phase detection error
    10.
    发明授权
    Phase detector with minimized phase detection error 失效

    公开(公告)号：US06340900B1

    公开(公告)日：2002-01-22

    申请号：US08582045

    申请日：1996-01-02

    申请人： Kevin S. Donnelly ,  Thomas H. Lee ,  Tsyr-Chyang Ho

    发明人： Kevin S. Donnelly ,  Thomas H. Lee ,  Tsyr-Chyang Ho

    IPC分类号： H03K526

    CPC分类号： G01R25/00 ,  H03L7/085

    摘要： A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.