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公开(公告)号：US06366122B1
公开(公告)日：2002-04-02
申请号：US09696856
申请日：2000-10-26
IPC分类号： H03K1900
CPC分类号： H03K19/018507 , H03K5/151 , H03K19/09429
摘要： A signal driver circuit uses a single power supply to provide differential low voltage swing signals for use in an integrated circuit. The driver reduces interconnect voltage swing and power consumption, while improving the speed performance of the interconnect. The driver includes series coupled drive transistors to provide differential signals on integrated circuit interconnects. The driver circuit can include circuitry to place the interconnects in a tri-state condition to allow for shared interconnects. An integrated circuit, such as a processor, includes first and second differential interconnects, a receiver circuit connected to the first and second differential interconnects for detecting a differential voltage provided thereon, and a driver circuit connected to the first and second differential interconnects for providing the differential voltage.
摘要翻译： 信号驱动器电路使用单个电源来提供用于集成电路的差分低电压摆幅信号。 驱动器降低互连电压摆幅和功耗，同时提高互连的速度性能。 驱动器包括串联耦合的驱动晶体管，以在集成电路互连上提供差分信号。 驱动器电路可以包括将互连置于三态条件以允许共享互连的电路。 诸如处理器的集成电路包括第一和第二差分互连，连接到第一和第二差分互连用于检测其上提供的差分电压的接收器电路，以及连接到第一和第二差分互连的驱动器电路，用于提供 差分电压。
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62.发明授权Integrated circuit bus architecture including a full-swing, clocked, common-gate receiver for fast on-chip signal transmission 有权集成电路总线架构，包括全频，时钟，共门接收器，用于快速片上信号传输公开(公告)号：US06353342B1
公开(公告)日：2002-03-05
申请号：US09702121
申请日：2000-10-30
IPC分类号： G11C706
CPC分类号： H04L25/0292 , H04L25/0278 , H04L25/028
摘要： An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.
摘要翻译： 公开了一种集成电路（IC）总线架构。 总线架构包括用于快速片上信号传输的接收器。 接收机包括具有连接到电压源的一个端子和可连接以接收感测信号的栅极端子的第一栅极器件。 第二栅极器件包括连接到第一栅极器件的另一个端子的一个端子，可连接的感测信号的栅极端子和用作接收器的输入端子的另一个端子，并且可连接到互连总线以从其它部件接收输入信号 在IC芯片上。 接收机还包括具有连接到电压源的一个端子和用作接收器的输出端的另一个端子并连接到第一门装置的另一端的第三门装置。 接收机还包括一个反相器，其具有连接到接收器的输出的输入端，并且具有连接到第三门装置的栅极端的输出端。 接收机的输入能够被预放电到低信号，并且接收机的输出能够被预充电到高信号，以便接收器接收的输入信号的基本瞬时传输。
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63.发明授权公开(公告)号：US06351150B1
公开(公告)日：2002-02-26
申请号：US09658793
申请日：2000-09-11
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/01855
摘要： A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.
摘要翻译： 利用动态驱动技术的高性能互连能够在低数据交换活动期间降低功耗。 提供了电路，其将动态驱动器电路中的评估操作的性能限制为时钟周期，在该周期期间，互连的当前输入位与先前的输入位不同。 因此，在低数据切换活动的时段期间，谨慎地执行驱动器输出的评估操作和随后的预充电。 还提供了一个输出电路，用于解码在其接收端处流经互连的数据流。 使用本发明的原理，可以通过使用静态CMOS技术的互连的交换活动来实现动态驱动器的性能优点。
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公开(公告)号：US06346831B1
公开(公告)日：2002-02-12
申请号：US09408190
申请日：1999-09-28
申请人： Ram K. Krishnamurthy , Lei Wang , Rajamohana Hegde
发明人： Ram K. Krishnamurthy , Lei Wang , Rajamohana Hegde
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： The invention involves a die having domino circuits. In some embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and at least one intermediate node. The domino stage has improved noise immunity and reduced leakage through reverse body biasing transistors in the evaluate network by raising voltage of the at least one intermediate node without static power consumption through the evaluate network. In other embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and wherein the domino stage further includes a diode transistor having a gate and an additional terminal connected to the domino stage output node. The diode transistor may resist leakage by operating in a subthreshold region to replenish charge on the domino stage output node and resists noise by turning on when small amounts of noise barely turn on transistors of the evaluate network.
摘要翻译： 本发明涉及具有多米诺骨牌电路的模具。 在一些实施例中，至少一些多米诺骨牌电路包括输出级和多米诺骨牌级，包括耦合到输出级的多米诺骨牌级输出节点。 多米诺骨牌阶段包括一个广泛评估网络，包括多米诺骨牌阶段输出节点和至少一个中间节点。 多米诺骨牌阶段通过评估网络提高至少一个中间节点的电压而无需静态功耗，从而提高了噪声抗扰度并减小了评估网络中反向偏置晶体管的泄漏。 在其他实施例中，至少一些多米诺骨牌电路包括输出级和多米诺骨牌级，包括耦合到输出级的多米诺骨牌级输出节点。 多米诺骨牌阶段包括包括多米诺骨牌阶段输出节点的广泛评估网络，并且其中多米诺骨牌阶段还包括具有连接到多米诺骨牌级输出节点的门和附加终端的二极管晶体管。 二极管晶体管可以通过在亚阈值区域中操作来抵抗泄漏，以补充多米诺骨牌级输出节点上的电荷，并且当少量噪声几乎不打开评估网络的晶体管时，通过接通来抵抗噪声。
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公开(公告)号：US06204696B1
公开(公告)日：2001-03-20
申请号：US09158410
申请日：1998-09-22
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is also coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provide therefrom an evaluated output signal. In other embodiments, the invention includes a domino circuit having a predischarge circuit coupled to a domino stage conductor. An evaluation path circuit includes source follower nFET devices coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provides therefrom an evaluated output signal. In still other embodiments, the invention includes a domino circuit having a precharge circuit including coupled to a domino stage conductor. An evaluation path circuit is coupled to the domino stage conductor. An output stage includes an inverter to receive a signal from the domino stage conductor and to provide an evaluated output signal on an output conductor, the output stage including a duplicate evaluation path circuit coupled to an output conductor.
摘要翻译： 在一些实施例中，本发明包括具有预充电电路的多米诺骨牌电路，该预充电电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。 评估路径电路也耦合到多米诺骨牌导体。 迟滞输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。 在其他实施例中，本发明包括具有耦合到多米诺骨牌导体的预放电电路的多米诺骨牌电路。 评估路径电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。 滞后输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。 在其他实施例中，本发明包括具有预充电电路的多米诺骨牌电路，其包括耦合到多米诺骨牌导体。 评估路径电路耦合到多米诺骨牌导体。 输出级包括反相器，用于从多米诺骨架导体接收信号并在输出导体上提供评估输出信号，输出级包括耦合到输出导体的重复评估路径电路。
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公开(公告)号：US20140105303A1
公开(公告)日：2014-04-17
申请号：US13649560
申请日：2012-10-11
IPC分类号： H04N7/32
CPC分类号： H04N19/43 , H04N19/567
摘要： In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.
摘要翻译： 根据一些实施例，可以减少使用Haar，SAD和Hadamard变换的运动估计算法的复杂度。 在一些实施例中，与现有技术相比可以减少求和的数量，并且可以用比较操作来替换一些现有的求和。 在一些实施例中，为了平衡延迟和面积或能量或功率考虑，用比较代替添加。
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公开(公告)号：US07275204B2
公开(公告)日：2007-09-25
申请号：US10954648
申请日：2004-09-30
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译： 移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。
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公开(公告)号：US06919737B2
公开(公告)日：2005-07-19
申请号：US10010737
申请日：2001-12-07
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018521
摘要： A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.
摘要翻译： 描述电压电平转换器和将第一逻辑电压电平转换到第二逻辑电压电平的方法。 在一个实施例中，电压电平转换器将连接到第一电源电压的第一逻辑单元连接到与第二电源电压连接的第二逻辑单元。 电压电平转换器包括连接到第二电源电压的至少一个晶体管。 所述至少一个晶体管具有其绝对值大于或等于所述第二电源电压和所述第一电源电压之间的差的绝对值的阈值电压。 在替代实施例中，用于将第一逻辑电压电平转换为第二逻辑电压电平的方法包括从具有在第一电压电平和第二电压电平之间的输出电压摆幅的逻辑单元传输逻辑信号，接收逻辑信号 在具有上拉晶体管的逻辑电路和在第三电压电平和第四电压电平之间的输出电压摆幅，并且当所述逻辑信号具有略大于所述第三电压 电平和第一电压电平。
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公开(公告)号：US06614279B2
公开(公告)日：2003-09-02
申请号：US09941457
申请日：2001-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
摘要翻译： 时钟接收器电路将从差分时钟分配介质接收的低幅度差分时钟信号分量转换成全摆幅数字时钟。 时钟接收器电路可以用作例如微电子器件内的管芯上的相关时钟分配系统的一部分。
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公开(公告)号：US06590801B2
公开(公告)日：2003-07-08
申请号：US10172106
申请日：2002-06-13
IPC分类号： G11C1140
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
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