公开(公告)号：US20210226037A1

公开(公告)日：2021-07-22

申请号：US17222608

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/51 ,  H01L29/417

Abstract: A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.

公开(公告)号：US11031395B2

公开(公告)日：2021-06-08

申请号：US16034520

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsu Ohtou ,  Ching-Wei Tsai ,  Jiun-Jia Huang ,  Kuan-Lun Cheng ,  Chi-Hsing Hsu

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/02

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

公开(公告)号：US20210151560A1

公开(公告)日：2021-05-20

申请号：US17135623

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, an isolation feature over the substrate, a first device fin protruding from the substrate and through the isolation feature, and a second device fin protruding from the substrate and through the isolation feature. The semiconductor device also includes a dielectric fin disposed between the first and second device fins and a metal gate stack engaging the first and second device fins. The dielectric fin separates the metal gate stack into first and second segments and provides electrical isolation between the first and second segments. A portion of the isolation feature is directly under a bottom surface of the dielectric fin.

公开(公告)号：US10971609B2

公开(公告)日：2021-04-06

申请号：US16549266

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Ching-Wei Tsai ,  Wang-Chun Huang ,  Kuan-Lun Cheng

IPC: H01L29/775 ,  H01L23/522 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.

公开(公告)号：US20210098459A1

公开(公告)日：2021-04-01

申请号：US17120637

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/308 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

公开(公告)号：US20210066137A1

公开(公告)日：2021-03-04

申请号：US16926470

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

公开(公告)号：US10937895B2

公开(公告)日：2021-03-02

申请号：US16201743

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/82 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238

Abstract: A method includes receiving a substrate; forming on the substrate a semiconductor fin; an isolation structure surrounding the semiconductor fin; and first and second dielectric fins above the isolation structure and sandwiching the semiconductor fin; depositing a spacer feature filling spaces between the semiconductor fin and the first and second dielectric fins; performing an etching process to recess the semiconductor fin, resulting in a trench between portions of the spacer feature; and epitaxially growing a semiconductor material in the trench.

公开(公告)号：US10930767B2

公开(公告)日：2021-02-23

申请号：US16387889

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

公开(公告)号：US10930569B2

公开(公告)日：2021-02-23

申请号：US16426660

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/82 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/12 ,  H01L27/088 ,  H01L27/06

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.

公开(公告)号：US10811317B2

公开(公告)日：2020-10-20

申请号：US16681621

申请日：2019-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

Abstract: Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming spacers on sidewalls of the second mask and patterning the semiconductor stack to form a first fin structure covered by the first mask structure and a second fin structure covered by the second mask structure and the spacers. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures. In addition, the second nanostructures are wider than the first nanostructures.