公开(公告)号：US07164525B2

公开(公告)日：2007-01-16

申请号：US11223227

申请日：2005-09-09

申请人： Ken-ichi Noda ,  Makoto Iwai ,  Takashi Yoshino

发明人： Ken-ichi Noda ,  Makoto Iwai ,  Takashi Yoshino

IPC分类号： G02F1/355

CPC分类号： G02F1/3551 ,  G02F1/377 ,  G02F2001/3505 ,  G02F2203/60

摘要： Wavelength conversion devices for converting fundamental waves to light of a different wavelength are provided. The devices have a wavelength converting layer comprising a plate-shaped body of a non-linear optical crystal having a first main face and a second main face. A supporting body is joined with the first main face of the wavelength converting layer. An additional supporting body may also be joined with the second main face of the wavelength converting layer.

摘要翻译： 提供了用于将基波转换成不同波长的光的波长转换装置。 这些器件具有包括具有第一主面和第二主面的非线性光学晶体的板状体的波长转换层。 支撑体与波长转换层的第一主面接合。 附加的支撑体也可以与波长转换层的第二主面接合。

公开(公告)号：US06181462B2

公开(公告)日：2001-01-30

申请号：US09321057

申请日：1999-05-27

申请人： Takashi Yoshino ,  Minoru Imaeda ,  Makoto Iwai

发明人： Takashi Yoshino ,  Minoru Imaeda ,  Makoto Iwai

IPC分类号： G02F202

CPC分类号： G02F1/377

摘要： A second harmonic wave-generation device for generating a second harmonic wave composed of an extraordinary ray from a fundamental wave composed of an ordinary ray, including a solid crystal of lithium potassium niobate-lithium potassium tantalate solid solution crystal or a single crystal made of lithium potassium niobate, wherein a mode field diameter of the fundamental wave inside the second harmonic wave-generation device is greater than that of the second harmonic wave.

摘要翻译： 一种二次谐波发生装置，用于产生由包含由铌酸锂钾 - 钽酸锂钾固溶体晶体构成的由普通射线构成的基波的特殊射线构成的二次谐波，或由锂构成的单晶 铌酸钾，其中二次谐波产生装置内的基波的模场直径大于二次谐波的模场直径。

公开(公告)号：US20110075485A1

公开(公告)日：2011-03-31

申请号：US12875794

申请日：2010-09-03

申请人： Koichi FUKUDA ,  Makoto Iwai

发明人： Koichi FUKUDA ,  Makoto Iwai

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5642 ,  G11C16/26

摘要： A non-volatile semiconductor storage device according to one aspect of the present invention includes a plurality of sense amplifier circuit that are configured to carry out a plurality of read cycles on a plurality of bit lines connected to those memory cells that are selected by a selected one of the word lines. During the second and subsequent read cycles, supply of a read current is ceased to those bit lines when it is determined in the preceding read cycle that a current not less than a certain determination current level flows therethrough, and the read current is supplied only to the remaining bit lines. A setup time of the bit lines in the first read cycle is set shorter than a setup time of the bit lines in the second and subsequent read cycles.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器件包括：多个读出放大器电路，被配置为在连接到被选择的那些存储器单元的多个位线上执行多个读取周期 一条字线。 在第二次和随后的读取周期期间，当在先前的读取周期中确定不小于某一确定电流电流的电流流过其中时，读取电流的供应停止到这些位线，并且仅将读取的电流提供给 剩下的位线。 第一读取周期中的位线的建立时间被设置为比第二和随后读取周期中位线的建立时间短。

公开(公告)号：US20110063911A1

公开(公告)日：2011-03-17

申请号：US12951616

申请日：2010-11-22

申请人： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

发明人： Makoto Iwai ,  Kazuhisa Kanazawa ,  Hiroshi Nakamura ,  Masaki Fujiu

IPC分类号： G11C16/04 ,  G11C16/16

CPC分类号： G11C16/16 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

公开(公告)号：US07903469B2

公开(公告)日：2011-03-08

申请号：US11838510

申请日：2007-08-14

申请人： Makoto Iwai ,  Yoshihisa Watanabe

发明人： Makoto Iwai ,  Yoshihisa Watanabe

IPC分类号： G11C16/26

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection transistor and a second selection transistor which are each connected to both ends of the plurality of memory cells respectively, a plurality of word lines and a plurality of bit lines which are connected to the plurality of memory cells and a data read control part wherein at least one of the memory cells is selected and when data is read from that memory cell a read pass voltage is applied to a word line which is connected to a non-selected memory cell other than the selected memory cell, and after applying the read pass voltage a voltage is applied to a control gate of the first selection transistor or the second selection transistor, and when applying the read pass voltage, the read pass voltage which is applied to the word line which is connected to at least one of the non-selected memory cells which is adjacent to the first selection transistor or the second selection transistor, is made lower than the read pass voltage which is applied to the word line which is connected to another cell of the non-selected memory cells.

摘要翻译： 非易失性半导体存储器包括存储单元阵列，该存储单元阵列具有多个与单元串联连接的NAND单元单元，第一选择晶体管和第二选择晶体管分别连接到多个存储器的两端 分别连接到多个存储单元的多个字线和多个位线，以及数据读取控制部分，其中至少一个存储器单元被选择，并且当从该存储器单元读取数据时读取 将通过电压施加到连接到除所选存储单元之外的未选择的存储单元的字线，并且在施加读取通过电压之后，将电压施加到第一选择晶体管或第二选择晶体管的控制栅极 ，并且当应用读通过电压时，施加到连接到未选择存储器中的至少一个的字线的读通过电压 使与第一选择晶体管或第二选择晶体管相邻的单元小于施加到连接到未选择的存储单元的另一单元的字线的读通过电压。

公开(公告)号：US07508712B2

公开(公告)日：2009-03-24

申请号：US11844096

申请日：2007-08-23

申请人： Makoto Iwai

发明人： Makoto Iwai

IPC分类号： G11C16/04

CPC分类号： G11C16/26

摘要： A nonvolatile semiconductor memory device includes a memory cell array 101 having a plurality memory strings, each of said plurality of memory strings having a plurality of memory cells connected in series, each of said plurality of memory cells having a control gate, said plurality of memory cells including a read-memory cell whose programmed data is read and a plurality of non-read-memory cells other than said read-memory cell, each said control gate of each said plurality of non-read-memory cells being applied with a read pass voltage to read said programmed data programmed in said read-memory cell, a read pass voltage application control part 201 for applying a predetermined read pass voltage to the control gates of all non-read memory cells among said plurality of memory cells other than a read-memory cell whose stored data are read, and a clock signal cycle control part 203 for controlling a cycle of a clock signal which is provided to said read pass voltage application control part 201.

摘要翻译： 非易失性半导体存储器件包括具有多个存储器串的存储单元阵列101，所述多个存储器串中的每一个具有串联连接的多个存储单元，所述多个存储单元中的每一个具有控制栅极，所述多个存储器 包括读取其编程数据的读取存储器单元和除所述读取存储单元之外的多个非读取存储单元的单元，每个所述多个非读取存储单元的所述控制栅极被应用于读取 读取所述读取存储单元中编程的所述编程数据的读出通过电压施加控制部201，用于将预定的读取通过电压施加到所述多个存储单元中除了 其存储的数据被读取的读出存储单元和用于控制提供给所述读取通过电压施加控制p的时钟信号的周期的时钟信号周期控制部分203 艺术201。

公开(公告)号：US07453625B2

公开(公告)日：2008-11-18

申请号：US11336308

申请日：2006-01-20

申请人： Shoichiro Yamaguchi ,  Makoto Iwai ,  Yuichi Iwata

发明人： Shoichiro Yamaguchi ,  Makoto Iwai ,  Yuichi Iwata

IPC分类号： G02F1/00 ,  G02F1/35

CPC分类号： G02F1/3558 ,  G02F1/3775

摘要： A comb electrode 3 is provided on a first main face 2a and a uniform electrode 4 is provided on a second main face 2b of a substrate made of a ferroelectric single crystal of a single domain, and a voltage is applied on the comb electrode 3 and the uniform electrode 4 to produce domain inversion part. It is laminated, on the substrate, an underlying substrate comprising a main body 5, a first conductive film 6 provided on a first main face 5a and a second conductive film 7 provided on a second main face 5b of the main body 5. The uniform electrode 4 is electrically conducted with the first conductive film 6 and a voltage is applied on the comb electrode 3 and the second conductive film 7 to form a domain inversion part in the substrate 2.

摘要翻译： 梳状电极3设置在第一主面2a上，并且均匀电极4设置在由单畴的铁电单晶构成的基板的第二主面2b上，并且电压施加在梳状电极 3和均匀电极4产生畴反转部分。 在基板上层叠下面的基板，该基板包括主体5，设置在第一主面5a上的第一导电膜6和设置在主体5的第二主表面5b上的第二导电膜7。 均匀电极4与第一导电膜6导电，并且在梳电极3和第二导电膜7上施加电压，以在基板2中形成畴反转部分。

公开(公告)号：US06513226B2

公开(公告)日：2003-02-04

申请号：US09817405

申请日：2001-03-26

申请人： Makoto Iwai ,  Makoto Ohmori ,  Takashi Yoshino

发明人： Makoto Iwai ,  Makoto Ohmori ,  Takashi Yoshino

IPC分类号： H01P1100

CPC分类号： C30B25/02 ,  C30B29/30 ,  Y10T29/49016

摘要： A film made of a single crystal of potassium lithium niobate is formed on a substrate made of a single crystal of potassium lithium niobate-potassium lithium tantalate solid solution. In this film formation, a temperature of the substrate is maintained in a range of 700° C.-850° C. and the film is formed by a metalorganic chemical vapor deposition method. By utilizing the film structure mentioned above, it is possible to generate a second harmonic wave in the optical waveguide with high efficiency.

摘要翻译： 在由铌酸钾锂 - 钽酸锂锂固溶体的单晶制成的基板上形成由铌酸锂锂的单晶制成的薄膜。 在该膜形成中，将基板的温度保持在700℃〜850℃的范围内，通过金属有机化学气相沉积法形成膜。 通过利用上述膜结构，可以高效率地在光波导中产生二次谐波。

公开(公告)号：US08642690B2

公开(公告)日：2014-02-04

申请号：US12521610

申请日：2007-12-28

申请人： Takeaki Saiki ,  Makoto Iwai ,  Haruhiko Furukawa ,  Anil Kumar Tomar

发明人： Takeaki Saiki ,  Makoto Iwai ,  Haruhiko Furukawa ,  Anil Kumar Tomar

IPC分类号： B60C1/00 ,  C08K5/24

CPC分类号： C07F7/1804

摘要： A bis[tri(hydroxypolyalkyleneoxy)silylalkyl] polysulfide, i.e., a polysulfide that contains bonded hydroxypolyalkyleneoxy groups instead of alkoxy groups in the bis(trialkoxysilylalkyl) polysulfide; a method of manufacturing of the aforementioned polysulfide by heating a bis(trialkoxysilylalkyl) polysulfide and a polyalkyleneglycol; a tire rubber additive to a tire rubber composition that comprises a bis[tri(hydroxypolyalkyleneoxy)silylalkyl] polysulfide alone or a mixture of bis[tri(hydroxypolyalkyleneoxy)silylalkyl] polysulfide and a polyalkyleneglycol; and a tire rubber composition that contains the aforementioned additive.

摘要翻译： 双（三（羟基聚亚烷氧基）甲硅烷基烷基]多硫化物，即在双（三烷氧基甲硅烷基烷基）多硫化物中含有键合的羟基聚亚烷基氧基代替烷氧基的多硫化物; 通过加热双（三烷氧基甲硅烷基烷基）多硫化物和聚亚烷基二醇制备上述多硫化物的方法; 包含单独的双[三（羟基亚烷基氧基）甲硅烷基烷基]多硫化物或双[三（羟基聚亚烷基氧基）甲硅烷基烷基]多硫化物和聚亚烷基二醇的混合物的轮胎橡胶组合物的轮胎橡胶添加剂; 和含有上述添加剂的轮胎橡胶组合物。

公开(公告)号：US08284605B2

公开(公告)日：2012-10-09

申请号：US12978878

申请日：2010-12-27

申请人： Rieko Tanaka ,  Makoto Iwai

发明人： Rieko Tanaka ,  Makoto Iwai

IPC分类号： G11C11/34

CPC分类号： G11C16/0408 ,  G11C16/26

摘要： An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell.

摘要翻译： 本发明的实施例提供一种包括NAND串，SEN节点和电容器的半导体存储装置。 NAND串包括多个串联存储单元，并且NAND串的一端连接到位线，而另一端连接到公共源极线。 SEN节点被配置为能够电连接到电压源和位线。 在电容器中，一端连接到SEN节点，而另一端连接到施加了预定范围内的电压的CLK节点。 只有当从多个存储单元中选择的所选择的存储单元是开小区时，通过减少SEN节点的放电期间的电容来增强SEN节点的放电率。