公开(公告)号：US20090154542A1

公开(公告)日：2009-06-18

申请号：US12002539

申请日：2007-12-17

申请人： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

发明人： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

摘要： Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

摘要翻译： 用于接收高速串行数据信号（例如，具有在约10Gpbs及更高的范围内的比特率）的电路包括仅具有两个串联连接级的两级连续时间线性均衡器。 可以提供相位检测器电路用于接收均衡器的串行输出，并将该输出中的连续比特对转换为连续并行形式的位对。 可以提供进一步的解复用电路以将并行形式位对的连续组分解成最终并行位组，在位数（例如，64个并行位）方面可能相当大。 本发明的另一方面涉及用于从相对大的并行数据比特组相对于高速串行数据输出信号有效地进行反向的多路复用器电路。

公开(公告)号：US07358883B1

公开(公告)日：2008-04-15

申请号：US11470343

申请日：2006-09-06

申请人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev

发明人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03M1/66

CPC分类号： G11C7/12 ,  G11C7/1045 ,  H03M1/662

摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that includes a plurality of register frames that are serially linked. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data is shifted into the primary register frame from a memory region that may be a ROM, RAM, soft IP of a PLD, an intelligent host or tester serial data input stream. A method for adjusting a signal through a bias circuit is also provided.

摘要翻译： 偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D2A）。 D2A耦合到包括多个串行连接的寄存器帧的主寄存器帧。 偏置电路包括还耦合到主寄存器框架的解码器。 还包括一个输出使能逻辑模块。 输出使能逻辑模块确定主寄存器何时具有完整数据集，因为数据从可能是ROM，RAM，PLD的软IP，智能主机或测试仪串行数据的存储器区域移入主寄存器帧 输入流。 还提供了一种通过偏置电路调整信号的方法。

公开(公告)号：US07245144B1

公开(公告)日：2007-07-17

申请号：US11169242

申请日：2005-06-27

申请人： Wilson Wong ,  Sergey Shumarayev

发明人： Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03K17/16

CPC分类号： H03K19/018564 ,  H03F3/45928 ,  H03F2203/45078 ,  H03F2203/45082 ,  H03F2203/45101 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03F2203/45154 ,  H03F2203/45222 ,  H03F2203/45541 ,  H03F2203/45566 ,  H03F2203/45626 ,  H03F2203/45681 ,  H03F2203/45686

摘要： Systems and methods are provided using common-mode-voltage bias circuitry to make common-mode-voltage adjustments to differential driver circuitry in integrated circuit differential communications links. Adjustable bias circuitry may be controlled using static and dynamic control signals. Dynamic control signals can be produced by core logic on a programmable logic device or other integrated circuit. Static control signals can be produced by programmable elements. Bias circuit adjustments made at one end of a differential link can be used to improve performance at either end of the link or can be used to improve power consumption or to balance power and performance considerations. The same integrated circuit design can be used in both AC-coupled and DC-coupled environments. The bias circuitry can be formed from an adjustable current source and adjustable resistor. The current source and adjustable resistors can be controlled by the same control signals.

摘要翻译： 使用共模电压偏置电路提供系统和方法，以对集成电路差分通信链路中的差分驱动器电路进行共模电压调整。 可调节的偏置电路可以使用静态和动态控制信号来控制。 动态控制信号可以由可编程逻辑器件或其他集成电路上的核心逻辑产生。 静态控制信号可以由可编程元件产生。 差分链路一端进行的偏置电路调整可用于提高链路两端的性能，或者可用于提高功耗或平衡功率和性能考虑。 同样的集成电路设计可用于交流耦合和直流耦合环境。 偏置电路可以由可调电流源和可调电阻器形成。 电流源和可调电阻可由相同的控制信号控制。

公开(公告)号：US20070014344A1

公开(公告)日：2007-01-18

申请号：US11182658

申请日：2005-07-14

申请人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

发明人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L25/03019

摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

公开(公告)号：US06864704B1

公开(公告)日：2005-03-08

申请号：US10669298

申请日：2003-09-24

申请人： Wilson Wong ,  Sergey Shumarayev

发明人： Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03K19/0185 ,  H04L25/02 ,  H03K17/16

CPC分类号： H04L25/0276 ,  H03K19/018564

摘要： Systems and methods are provided using common-mode-voltage bias circuitry to make common-mode-voltage adjustments to differential driver circuitry in integrated circuit differential communications links. Adjustable bias circuitry may be controlled using static and dynamic control signals. Dynamic control signals can be produced by core logic on a programmable logic device or other integrated circuit. Static control signals can be produced by programmable elements. Bias circuit adjustments made at one end of a differential link can be used to improve performance at either end of the link or can be used to improve power consumption or to balance power and performance considerations. The same integrated circuit design can be used in both AC-coupled and DC-coupled environments. The bias circuitry can be formed from an adjustable current source and adjustable resistor. The current source and adjustable resistors can be controlled by the same control signals.

公开(公告)号：US08831140B2

公开(公告)日：2014-09-09

申请号：US11687052

申请日：2007-03-16

申请人： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

发明人： Allen Chan ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H04L27/00 ,  H03K19/177 ,  G06F13/38 ,  H04L5/14

CPC分类号： G06F13/385 ,  H03K19/177 ,  H03K19/17744 ,  H04L5/1446

摘要： Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.

摘要翻译： 用于可编程逻辑器件中的高速串行接口的自动速率协商逻辑确定单个位转换的多次出现（即，从“0”到“1”到“0”或从“1”到“1”的数据转换 0“到”1“）发生在高速串行接口的数据信道上的预定时间间隔内。 间隔优选地被选择为使得多次出现单位转换意味着数据信道以全速率模式运行。 速率协商逻辑可以在接口中共享具有时钟数据恢复电路的相位检测器。 相位检测器可以是专门用于检测单位转换的爆发相位检测器。

公开(公告)号：US08669828B1

公开(公告)日：2014-03-11

申请号：US12909739

申请日：2010-10-21

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC分类号： H04B3/28

CPC分类号： H01L23/642 ,  H01L2924/0002 ,  H05K1/0231 ,  H01L2924/00

摘要： Integrated circuits with decoupling capacitor circuitry are provided. Decoupling capacitor circuitry may include multiple arrays of decoupling capacitors. Each decoupling capacitor array may have a corresponding decoupling capacitor monitoring circuit that is associated with that decoupling capacitor array. Each decoupling capacitor monitoring circuit may include a resistor and switching circuitry. Each decoupling capacitor monitoring circuit may be coupled to a comparator and control circuitry. During testing, the control circuitry may configure each decoupling capacitor array for leakage current testing one at a time. If a decoupling capacitor array is determined to exhibit excessive leakage currents, that decoupling capacitor array will be marked as defective and will be disabled from use. If the decoupling capacitor array is determined to exhibit tolerable leakage currents, that decoupling capacitor array will be enable for use to help reduce power supply noise.

摘要翻译： 提供具有去耦电容电路的集成电路。 去耦电容器电路可以包括多个去耦电容器阵列。 每个去耦电容器阵列可以具有与该去耦电容器阵列相关联的相应的去耦电容器监控电路。 每个去耦电容器监控电路可以包括电阻器和开关电路。 每个去耦电容器监控电路可以耦合到比较器和控制电路。 在测试期间，控制电路可以配置每个去耦电容器阵列以便一次一个地进行漏电流测试。 如果解耦电容器阵列被确定为表现出过多的漏电流，则该去耦电容阵列将被标记为有缺陷的并且将被禁止使用。 如果解耦电容器阵列被确定为表现出可容忍的漏电流，则该去耦电容器阵列将被用于帮助减少电源噪声。

公开(公告)号：US08111784B1

公开(公告)日：2012-02-07

申请号：US12082483

申请日：2008-04-11

申请人： Weiqi Ding ,  Mingde Pan ,  Wilson Wong ,  Sergey Shumarayev ,  Peng Li

发明人： Weiqi Ding ,  Mingde Pan ,  Wilson Wong ,  Sergey Shumarayev ,  Peng Li

IPC分类号： H04L25/06

CPC分类号： H04L25/063

摘要： Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.

摘要翻译： 用于收集关于高速串行数据信号的眼睛的信息的方法和装置包括在几个眼睛切片位置采样重复的多位数据模式的每一位。 对于任何给定的眼片位置，将数据模式中的每个位在电压中与基线参考信号电压进行比较，以建立该位的参考值。 然后在重复电压比较时，参考信号电压逐渐增加，直到比较结果的一些位与该位的参考值不同。 这在眼部切片位置建立了眼睛的上限值。 然后，参考信号电压逐渐减小，以类似地找到该眼片的较低值。

公开(公告)号：US20110211621A1

公开(公告)日：2011-09-01

申请号：US13103132

申请日：2011-05-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04L5/14 ,  H04L27/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07924184B1

公开(公告)日：2011-04-12

申请号：US11904008

申请日：2007-09-24

申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

IPC分类号： H03M9/00

CPC分类号： H03K19/1732

摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.

摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和高速串行数据信号接口（例如，收发器）电路的通道。 为了使集成电路能够支持许多可能的不同高速串行通信协议中的任何一种，该信道被硬接线以包括用于与可编程电路交换并行数据的固定宽度的并行数据总线。 无论正在执行协议，始终使用该总线的全宽。 可编程电路的一部分被编程为在块宽度和组宽度之间转换数据，其可以与块宽度不同，并且用于集成电路中其他地方的数据。