公开(公告)号：US07488645B2

公开(公告)日：2009-02-10

申请号：US10907707

申请日：2005-04-13

申请人： Tzyh-Cheang Lee

发明人： Tzyh-Cheang Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/792

摘要： A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control gate and a cap layer. Next, a plurality of spacers is formed on the sidewalls of the stack structures. Thereafter, a gate dielectric layer is formed over the substrate. A word line is formed between two neighboring stack structures. After that, the cap layers in the stack structures are removed. A source and a drain are formed in the substrate beside the stack structures adjacent to the sides of each word line.

摘要翻译： 描述非易失性存储器及其制造方法。 首先，提供基板。 然后，在基板上形成多个堆叠结构。 每个堆叠结构从底部到顶部包括底部电介质层，电荷俘获层，顶部电介质层，控制栅极和盖层。 接下来，在堆叠结构的侧壁上形成多个间隔物。 此后，在衬底上形成栅极电介质层。 在两个相邻堆叠结构之间形成字线。 之后，去除堆叠结构中的盖层。 在与每个字线的侧面相邻的堆叠结构旁边的基板中形成源极和漏极。

公开(公告)号：US07485533B2

公开(公告)日：2009-02-03

申请号：US11549639

申请日：2006-10-14

申请人： Tzyh-Cheang Lee

发明人： Tzyh-Cheang Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/7923

摘要： A non-volatile memory cell is provided. The non-volatile memory includes a substrate, a gate stacked layer, an isolation layer and a conductive layer. The gate stacked layer includes a tunneling layer, a charge trapping layer, a barrier layer and a control gate layer sequentially stacked over the substrate, and the stacked gate layer has an opening therein through these layers. The isolation layer is located on the surface of the opening. The conductive layer is disposed in the opening to cover the isolation layer.

摘要翻译： 提供非易失性存储单元。 非易失性存储器包括衬底，栅层叠层，隔离层和导电层。 栅极层叠层包括依次层叠在基板上的隧道层，电荷俘获层，势垒层和控制栅极层，并且堆叠的栅极层通过这些层具有开口。 隔离层位于开口的表面上。 导电层设置在开口中以覆盖隔离层。

公开(公告)号：US20080266931A1

公开(公告)日：2008-10-30

申请号：US11739942

申请日：2007-04-25

申请人： Denny Tang ,  Tai-Bor Wu ,  Wen-Yuan Chang ,  Tzyh-Cheang Lee

发明人： Denny Tang ,  Tai-Bor Wu ,  Wen-Yuan Chang ,  Tzyh-Cheang Lee

IPC分类号： G11C11/24 ,  G11C11/00

CPC分类号： G11C11/16 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/55

摘要： Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.

摘要翻译： 这里公开了具有包围介电层的一个或多个缓冲层的新的电阻式存储器件。 通过在器件的介电层周围插入一个或多个缓冲层，器件的电阻比被高度提高。 例如，使用这种独特的堆叠结构的测试显示出比电阻式存储器件中发现的常规电极 - 电介质电极堆叠结构大约1000倍的电阻比。 电阻式存储器件的电阻比的这种改进被认为是来自缓冲层和电介质层之间的改进的界面相干性，从而更平滑的形貌。

公开(公告)号：US20070272970A1

公开(公告)日：2007-11-29

申请号：US11838893

申请日：2007-08-15

申请人： Tzyh-Cheang Lee

发明人： Tzyh-Cheang Lee

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/792

摘要： A non-volatile memory and a method of fabricating the same are described. First, a substrate is provided. Then, a plurality of stack structures is formed on the substrate. Each stack structure comprises, from bottom to top, a bottom dielectric layer, a charge trapping layer, a top dielectric layer, a control gate and a cap layer. Next, a plurality of spacers is formed on the sidewalls of the stack structures. Thereafter, a gate dielectric layer is formed over the substrate. A word line is formed between two neighboring stack structures. After that, the cap layers in the stack structures are removed. A source and a drain are formed in the substrate beside the stack structures adjacent to the sides of each word line.

摘要翻译： 描述非易失性存储器及其制造方法。 首先，提供基板。 然后，在基板上形成多个堆叠结构。 每个堆叠结构从底部到顶部包括底部电介质层，电荷俘获层，顶部电介质层，控制栅极和盖层。 接下来，在堆叠结构的侧壁上形成多个间隔物。 此后，在衬底上形成栅极电介质层。 在两个相邻堆叠结构之间形成字线。 之后，去除堆叠结构中的盖层。 在与每个字线的侧面相邻的堆叠结构旁边的基板中形成源极和漏极。

公开(公告)号：US20070045722A1

公开(公告)日：2007-03-01

申请号：US11218090

申请日：2005-08-31

申请人： Tzyh-Cheang Lee

发明人： Tzyh-Cheang Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A non-volatile memory cell is described, including a semiconductor body of a first conductivity type, a trapping layer, a gate, and a first to a third doped regions of a second conductivity type. The semiconductor body has a trench thereon, the trapping layer is disposed on the surface of the trench, and the gate is disposed in the trench. The first doped region is located in the semiconductor body under the trench, and the second and third doped regions are located in the semiconductor body at two sides of the trench. A non-volatile memory array based on the memory cell, a method for fabricating the memory cell and a method for fabricating the non-volatile memory array are also described.

摘要翻译： 描述了非易失性存储单元，其包括第一导电类型的半导体本体，俘获层，栅极和第二至第三第二导电类型的掺杂区域。 半导体本体上具有沟槽，捕获层设置在沟槽的表面上，并且栅极设置在沟槽中。 第一掺杂区域位于沟槽下的半导体本体中，并且第二和第三掺杂区域位于沟槽两侧的半导体本体中。 还描述了基于存储器单元的非易失性存储器阵列，用于制造存储单元的方法和用于制造非易失性存储器阵列的方法。

公开(公告)号：US20060208306A1

公开(公告)日：2006-09-21

申请号：US10907006

申请日：2005-03-16

申请人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

发明人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

摘要： The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

摘要翻译： 单多晶硅EEPROM包括串联连接到第二PMOS晶体管的第一PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括浮置栅极，第一P + +掺杂漏极区域和第一P + +掺杂源极区域。 第二PMOS晶体管包括栅极和第二P + +掺杂源极区域。 第一PMOS晶体管的第一P + SUP掺杂漏区用作第二PMOS晶体管的漏极。 二极管位于包括P阱和N + +掺杂区的P型衬底中。 浮栅与N阱重叠并延伸到N + +掺杂区。 浮置栅极下面的P阱和N + + / / P>掺杂区域结的重叠区域用作第一PMOS晶体管附近的雪崩注入点。

公开(公告)号：US20050132549A1

公开(公告)日：2005-06-23

申请号：US10853459

申请日：2004-05-25

申请人： Wong-Cheng Shih ,  Wen-Chi Ting ,  Tzyh-Cheang Lee ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

发明人： Wong-Cheng Shih ,  Wen-Chi Ting ,  Tzyh-Cheang Lee ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01G9/00

CPC分类号： H01L28/40 ,  H01L21/31604 ,  H01L28/56 ,  Y10T29/43 ,  Y10T29/435

摘要： A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.

摘要翻译： 实现了制造具有高介电常数绝缘体并夹在宽带隙绝缘体之间的金属绝缘体金属（MIM）电容器的方法，导致低漏电流和每单位面积的高电容。 高k层增加下一代混合信号器件的单位面积电容，而宽带绝缘子减少泄漏电流。 在第二实施例中，在宽带绝缘体之间形成不同的高k材料的多层以大大增加每单位面积的电容。 优化了层材料和厚度，以减少非线性电容对电压的依赖性。

公开(公告)号：US06878988B1

公开(公告)日：2005-04-12

申请号：US10709854

申请日：2004-06-02

申请人： Tzyh-Cheang Lee ,  Nai-Chen Peng ,  Chungchin Shih ,  Ching-Hung Cheng

发明人： Tzyh-Cheang Lee ,  Nai-Chen Peng ,  Chungchin Shih ,  Ching-Hung Cheng

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/792

摘要： An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.

摘要翻译： 提供电可编程的非易失性存储单元。 制备半导体衬底。 在半导体衬底上限定一对间隔开的源极/漏极（S / D）区域。 间隔开的S / D区域在其间限定通道区域。 诸如二氧化硅的第一电介质层设置在S / D区域上。 辅助栅极层叠在第一电介质层上。 辅助门具有顶表面和侧壁。 包括电荷捕获层的第二介电层均匀地设置在辅助栅极的顶表面和侧壁上，并且还设置在沟道区上。 第二电介质层在S / D区域之间提供凹槽。 导电栅极材料填充凹槽以控制所述沟道区域。

公开(公告)号：US06559493B2

公开(公告)日：2003-05-06

申请号：US10167864

申请日：2002-06-11

申请人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

发明人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

IPC分类号： H01L31119

CPC分类号： H01L28/90 ,  Y10S438/957

摘要： A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.

摘要翻译： 在第一电介质层中形成第一金属插头。 产生独立的第二金属插头，其与第一金属插头对准并与第一金属插头接触，延伸第一金属插头。 第二个金属插塞由已经在蚀刻停止层和电介质层上形成的开口围绕。 电容器电介质层沉积在第一和第二金属插头的暴露表面和围绕第二插头的开口的内表面中。 在蚀刻停止层和电介质层的开口内部的电容器电介质上形成一层金属。