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    SEMICONDUCTOR PROCESS
    61.
    发明申请
    SEMICONDUCTOR PROCESS 审中-公开
    半导体工艺

    公开(公告)号：US20170005007A1

    公开(公告)日：2017-01-05

    申请号：US15268630

    申请日：2016-09-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Kuo Chiang ,  Chun-Hsien Lin

    IPC: H01L21/8234 ,  H01L29/423 ,  H01L21/02 ,  H01L29/51

    CPC classification number: H01L21/823462 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/0228 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    Abstract: A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is lower than the energy bandgap of the first metal oxide layer and that of the third metal oxide layer. The semiconductor structure includes a metal oxide layer on a substrate, wherein the energy bandgap of the metal oxide layer changes along a direction perpendicular to the surface of the substrate. The present invention also provides a semiconductor process forming said semiconductor structure.

    Abstract translation: 半导体结构包括在基板上的堆叠的金属氧化物层，其中堆叠的金属氧化物层包括从顶部到底部的第一金属氧化物层，第二金属氧化物层和第三金属氧化物层，以及第二金属氧化物层的能带隙 金属氧化物层比第一金属氧化物层和第三金属氧化物层的能带隙低。 半导体结构包括在基板上的金属氧化物层，其中金属氧化物层的能带隙沿着垂直于衬底表面的方向改变。 本发明还提供了形成所述半导体结构的半导体工艺。

    Manufacturing Method of Metal Oxide Semiconductor Transistor
    63.
    发明申请
    Manufacturing Method of Metal Oxide Semiconductor Transistor 有权
    金属氧化物半导体晶体管的制造方法

    公开(公告)号：US20160079071A1

    公开(公告)日：2016-03-17

    申请号：US14941648

    申请日：2015-11-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Tai Chiang ,  Chun-Hsien Lin

    IPC: H01L21/285 ,  H01L21/28

    CPC classification number: H01L21/28518 ,  H01L21/28008 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/41725 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

    Abstract: A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

    Abstract translation: MOS晶体管的制造方法中，MOS晶体管包括基板，栅极氧化物，栅极，源极/漏极区域和硅化物层。 栅极氧化物设置在衬底上，并且栅极设置在栅极氧化物上。 源极/漏极区域设置在栅极两侧的衬底中。 硅化物层设置在源极/漏极区域上，其中硅化物层包括弯曲的底部表面和弯曲的顶部表面，弯曲的顶部表面和弯曲的底部表面都朝向衬底弯曲，并且弯曲的顶部表面从两个凹陷 侧面，硅化物层尖端的两端在源极/漏极区域上升起，中间的硅化物层比外围的硅化物层厚，从而形成新月形结构。 本发明还提供一种MOS晶体管的制造方法。

    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF
    65.
    发明申请
    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
    具有金属门的半导体器件及其制造方法

    公开(公告)号：US20140127892A1

    公开(公告)日：2014-05-08

    申请号：US14135520

    申请日：2013-12-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

    IPC: H01L21/8238

    CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

    Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

    SEMICONDUCTOR STRUCTURE
    66.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权
    半导体结构

    公开(公告)号：US20140077229A1

    公开(公告)日：2014-03-20

    申请号：US14089771

    申请日：2013-11-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

    IPC: H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

    Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

    Abstract translation: 非平面半导体结构包括衬底，衬底上的至少一个翅片结构，鳍覆盖部分的鳍结构和衬底的一部分，使得鳍结构被分成与栅极和源极/漏极堆叠的沟道区域， 漏极区域，覆盖在鳍状结构的源极/漏极区域上的多个外延结构，在鳍状结构的沟道区域和外延结构之间设置凹部，以及形成在侧壁上的间隔物 的栅极和外延结构，其中填充在凹槽中的间隔物的部分与外延结构的顶表面齐平。

    SEMICONDUCTOR DEVICE
    67.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250142815A1

    公开(公告)日：2025-05-01

    申请号：US18519092

    申请日：2023-11-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Wen-Chieh Chang ,  Kun-Szu Tseng ,  Sheng-Yuan Hsueh ,  Yao-Jhan Wang

    IPC: H10B20/25

    Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.

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