-
61.发明申请Data subscribe-and-publish mechanisms and methods for producer-consumer pre-fetch communications 有权用于生产者 - 消费者预取通信的数据订阅和发布机制和方法公开(公告)号：US20100241813A1
公开(公告)日：2010-09-23
申请号：US11493441
申请日：2006-07-26
申请人： Xiaowei Shen
发明人： Xiaowei Shen
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/52 , G06F9/544 , G06F12/0831 , G06F2212/507
摘要： A system supporting producer-consumer pre-fetch communications includes a first processor, wherein the first processor is a producer node, and a second processor, wherein the second processor is a consumer node. The system further includes a data subscribe mechanism for performing a data subscribe operation at the consumer node, wherein the data subscribe operation records that a memory address is subscribed at the consumer node, a data publish mechanism for performing a data publish operation at the producer nod; wherein the data publish operation sends data of the memory address from the producer node to the consumer node if the memory address is subscribed at the consumer node, and a communication network coupled to the producer node and the consumer node for enabling communicating between the producer node and the consumer node.
摘要翻译： 支持生产者 - 消费者预取通信的系统包括第一处理器，其中第一处理器是生产者节点和第二处理器，其中第二处理器是消费者节点。 该系统还包括用于在消费者节点处执行数据订阅操作的数据订阅机制，其中数据订阅操作记录消费者节点处的存储器地址被订阅的数据发布机制，用于在生产者节点处执行数据发布操作 ; 其中如果在所述消费者节点处订阅了所述存储器地址，则所述数据发布操作将所述存储器地址的数据从所述生产者节点发送到所述消费者节点;以及耦合到所述生产者节点和所述消费者节点的通信网络，用于实现所述生产者节点 和消费者节点。
-
公开(公告)号：US07676637B2
公开(公告)日：2010-03-09
申请号：US10833197
申请日：2004-04-27
申请人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
发明人： Xiaowei Shen , Jaehyuk Huh , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , Y02D10/13
摘要： In shared-memory multiprocessor systems, cache interventions from different sourcing caches can result in different cache intervention costs. With location-aware cache coherence, when a cache receives a data request, the cache can determine whether sourcing the data from the cache will result in less cache intervention cost than sourcing the data from another cache. The decision can be made based on appropriate information maintained in the cache or collected from snoop responses from other caches. If the requested data is found in more than one cache, the cache that has or likely has the lowest cache intervention cost is generally responsible for supplying the data. The intervention cost can be measured by performance metrics that include, but are not limited to, communication latency, bandwidth consumption, load balance, and power consumption.
摘要翻译： 在共享内存多处理器系统中，来自不同采购缓存的缓存干预可能导致不同的缓存干预成本。 利用位置感知高速缓存一致性，当缓存接收到数据请求时，高速缓存可以确定从高速缓存中提取数据是否会导致比从另一高速缓存提供数据更少的高速缓存干预成本。 该决定可以基于保存在缓存中的适当信息或从其他缓存的窥探响应收集。 如果在多个缓存中找到所请求的数据，则具有或可能具有最低缓存干预成本的高速缓存通常负责提供数据。 干预成本可以通过包括但不限于通信延迟，带宽消耗，负载平衡和功耗的性能指标来衡量。
-
63.发明申请公开(公告)号：US20090178052A1
公开(公告)日：2009-07-09
申请号：US11491413
申请日：2006-07-21
CPC分类号： G06F12/0842 , G06F2212/271
摘要： A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data. Information as to which banks store which data may also be provided, for example, by the hardware. This information may be used to schedule threads on one or more cores. A selected bank in cache memory may be reserved strictly for selected data.
摘要翻译： 提供了一种用于在非均匀缓存体系结构中进行延迟识别的线程调度的系统和方法。 可以向硬件提供指令，指定哪些存储体存储数据。 关于哪些银行存储哪些数据的信息也可以由硬件提供。 该信息可用于在一个或多个核心上调度线程。 高速缓冲存储器中的选定存储区可能被严格保留用于所选数据。
-
64.发明申请Method and System for Handling Transaction Buffer Overflow In A Multiprocessor System 有权在多处理器系统中处理事务缓冲区溢出的方法和系统公开(公告)号：US20090144524A1
公开(公告)日：2009-06-04
申请号：US12325866
申请日：2008-12-01
申请人： Xiaowei Shen , Hua Yong Wang , Kun Wang
发明人： Xiaowei Shen , Hua Yong Wang , Kun Wang
CPC分类号： G06F9/466 , G06F9/526 , G06F12/0815 , G06F12/0842 , G06F12/0893
摘要： There is disclosed a method and apparatus for handling transaction buffer overflow in a multi-processor system as well as a transaction memory system in a multi-processor system. The method comprises the steps of: when overflow occurs in a transaction buffer of one processor, disabling peer processors from entering transactions, and waiting for any processor having a current transaction to complete its current transaction; re-executing the transaction resulting in the transaction buffer overflow without using the transaction buffer; and when the transaction execution is completed, enabling the peer processors for entering transactions.
摘要翻译： 公开了一种在多处理器系统中处理事务缓冲器溢出以及多处理器系统中的事务存储器系统的方法和装置。 该方法包括以下步骤：当在一个处理器的事务缓冲器中发生溢出时，禁止对等处理器进入事务，并等待具有当前事务的任何处理器完成其当前事务; 重新执行事务导致事务缓冲区溢出而不使用事务缓冲区; 并且当事务执行完成时，使对等体处理器能够进行事务处理。
-
65.发明申请公开(公告)号：US20080263278A1
公开(公告)日：2008-10-23
申请号：US12130752
申请日：2008-05-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译： 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。
-
公开(公告)号：US07343454B2
公开(公告)日：2008-03-11
申请号：US10989755
申请日：2004-11-16
申请人： Xiaowei Shen
发明人： Xiaowei Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0815
摘要： We present a triangle ordering mechanism that maintains triangle ordering of coherence messages in SMP systems. If cache A sends a multicast message to caches B and C, and if cache B sends a message to cache C after receiving and processing the multicast message from cache A, the triangle ordering mechanism ensures that cache C processes the multicast message from cache A before processing the message from cache B. The triangle ordering mechanism enables efficient snoopy cache coherence in SMP systems in which caches communicate with each other via message-passing networks. A modified version of the triangle ordering mechanism categorizes coherence messages into non-overlapping sequencing classes, and ensures triangle ordering for coherence messages in the same sequencing class. The modified triangle ordering mechanism can significantly reduce potential performance degradation due to false waiting.
摘要翻译： 我们提出一种维护SMP系统中相干消息的三角形排序的三角形排序机制。 如果缓存A向缓存B和C发送多播消息，并且如果缓存B在从高速缓存A接收并处理多播消息之后向高速缓存C发送消息，则三角排序机制确保高速缓存C在高速缓存A之前处理来自高速缓存A的多播消息 处理来自高速缓存B的消息。三角排序机制使得高速缓存在SMP系统中的高速缓存一致性，其中高速缓存通过消息传递网络彼此通信。 三角形排序机制的修改版本将相干消息分类为非重叠排序类，并确保相同排序类中的相干消息的三角形排序。 改进的三角形排序机制可以显着降低由于假等待引起的潜在性能下降。
-
67.发明申请Mechanism to save and restore cache and translation trace for fast context switch 有权用于快速上下文切换的保存和恢复缓存和转换跟踪的机制公开(公告)号：US20080010442A1
公开(公告)日：2008-01-10
申请号：US11481515
申请日：2006-07-06
IPC分类号： G06F9/44
CPC分类号： G06F9/461
摘要： A method and system for efficient context switching are provided. An execution entity that is to be context switched out is allowed to continue executing for a predetermined period of time before being context switched out. During the predetermined period of time in which the execution entity continues to execute, the hardware or an operating system tracks and records its footprint such as the addresses and page and segment table entries and the like accessed by the continued execution. When the execution entity is being context switched back in, its page and segment table and cache states are reloaded for use in its immediate execution.
摘要翻译： 提供了一种用于高效上下文切换的方法和系统。 允许上下文切换的执行实体在上下文切换之前继续执行预定时间段。 在执行实体继续执行的预定时间段期间，硬件或操作系统跟踪并记录其持续执行访问的地址和页面和段表项等的占用空间。 当执行实体正在上下文切换回来时，其页面和段表格和高速缓存状态被重新加载以用于其立即执行。
-
68.发明申请公开(公告)号：US20080010408A1
公开(公告)日：2008-01-10
申请号：US11481020
申请日：2006-07-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译： 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。
-
公开(公告)号：US07308538B2
公开(公告)日：2007-12-11
申请号：US10981370
申请日：2004-11-04
申请人： Xiaowei Shen
发明人： Xiaowei Shen
CPC分类号： G06F12/0826 , G06F12/0831
摘要： With scope-based cache coherence, a cache can maintain scope information for a memory address. The scope information specifies caches in which data of the address is potentially cached, but not necessarily caches in which data of the address is actually cached. Appropriate scope information can be used as snoop filters to reduce unnecessary coherence messages and snoop operations in SMP systems. If a cache maintains scope information of an address, it can potentially avoid sending cache requests to caches outside the scope in case of a cache miss on the address. Scope information can be adjusted dynamically via a scope calibration operation to reflect changing data access patterns. A calibration prediction mechanism can be employed to predict when a scope calibration needs to be invoked.
摘要翻译： 使用基于范围的缓存一致性，缓存可以维护存储器地址的范围信息。 范围信息指定缓存，其中地址的数据可能被高速缓存，但不一定是高速缓存，其中地址的数据实际上被缓存。 适当的范围信息可以用作窥探过滤器，以减少SMP系统中不必要的一致性消息和窥探操作。 如果缓存维护地址的范围信息，则在地址上存在高速缓存未命中的情况下，可能会避免向高速缓存发送缓存请求。 范围信息可以通过示波器校准操作动态调整，以反映不断变化的数据访问模式。 校准预测机制可用于预测何时需要调用范围校准。
-
公开(公告)号：US20060265542A1
公开(公告)日：2006-11-23
申请号：US11131972
申请日：2005-05-18
申请人： Xiaowei Shen , Yefim Shuf , Peter Sweeney
发明人： Xiaowei Shen , Yefim Shuf , Peter Sweeney
CPC分类号： G06F12/0862 , G06F11/3409 , G06F11/3471 , G06F11/348 , G06F12/12 , G06F2201/885 , G06F2212/6028
摘要： Systems and methods for cache replacement monitoring (CRM) are provided. The system includes a monitored cache comprising a monitored cache line set, the monitored cache line set comprising at least one cache line capable of holding data of a monitored address; and a CRM mechanism operatively associated with the monitored cache. The CRM mechanism collects CRM information for the monitored address. The method includes the steps of collecting CRM information for a monitored address in a monitored cache; and recording the CRM information for the monitored address, when at least one of (1) the monitored address is cached in the monitored cache, (2) the monitored address is replaced in the monitored cache, (3) any cache line in a cache line set corresponding to the monitored address is cached in the monitored cache, and (4) any cache line in a cache line set corresponding to the monitored address is replaced in the monitored cache.
摘要翻译： 提供了缓存替换监控（CRM）的系统和方法。 所述系统包括被监视的高速缓存，包括被监视的高速缓存行集合，所述监视的高速缓存行集合包括能够保存被监视地址的数据的至少一个高速缓存行; 以及与所监视的缓存可操作地相关联的CRM机制。 CRM机制收集受监控地址的CRM信息。 该方法包括以下步骤：在受监视的高速缓存中收集被监视地址的CRM信息; 以及（1）所监视的地址中的至少一个被缓存在被监视的高速缓存中时，记录所监视的地址的CRM信息，（2）被监视的地址被替换为被监视的高速缓存，（3）高速缓存中的任何高速缓存行 对应于被监视地址的线路组被缓存在被监视的高速缓存中，并且（4）在被监视的高速缓存中替换与所监视的地址相对应的高速缓存行集合中的任何高速缓存行。
-
-
-
-
-
-
-
-
-
搜索结果
86 条记录 (耗时 0.023 秒)
