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61.发明授权公开(公告)号：US08320439B2
公开(公告)日：2012-11-27
申请号：US12040575
申请日：2008-02-29
IPC分类号： H03H7/30
CPC分类号： H04L25/03006 , H04L25/03343 , H04L2025/0377 , H04L2025/03808
摘要： Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.
摘要翻译： 为自适应链路伙伴发射机均衡提供了方法和装置。 根据本发明的一个方面，本地收发器通过在链路伙伴和本地收发信机之间的信道上接收训练帧来适配链路伙伴的一个或多个均衡参数，其中训练帧由预定义的训练模式组成; 调整所述链路伙伴的一个或多个均衡参数; 以及基于所述本地收发器是否适当地接收了所述预定训练模式，确定所述信道的均衡是否满足一个或多个预定标准。 预定义的训练模式可以是伪随机模式，例如PN11模式，可以可选地提高通道的噪声余量和抖动余量。
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62.发明申请公开(公告)号：US20120068762A1
公开(公告)日：2012-03-22
申请号：US13304759
申请日：2011-11-28
IPC分类号： H02J4/00
CPC分类号： H02J1/00
摘要： Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.
摘要翻译： 公开了一种用于通过电源电路来调节提供给IC的电压的电路，该电源电路基于由电阻分压器产生的输出控制信号产生调节输出电压。 电路包括配置成产生接口控制信号的PVT检测器和连接到PVT检测器和电阻分压器的接口电路（i），以及（ii）被配置为响应于接口控制信号调整其电阻。 调整接口电路的电阻可以调节输出控制信号的电压，从而使电源电路调整稳压输出电压。
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63.发明申请公开(公告)号：US20120027073A1
公开(公告)日：2012-02-02
申请号：US12847700
申请日：2010-07-30
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0356 , H04L2025/03617 , H04L2025/03796
摘要： Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.
摘要翻译： 提供方法和装置用于适应具有可编程自适应模式的连续时间 - 决策反馈均衡器。 通过获得触发连续时间判定反馈均衡器的极点和增益中的一个或多个的自适应的至少一个可编程签名模式来适配连续时间判定反馈均衡器; 检测输入信号中的至少一个可编程签名模式; 以及当在所述输入信号中检测到所述至少一个可编程签名模式时，使所述连续时间判定反馈均衡器的极点和增益中的一个或多个被适配。 可以选择可编程签名模式，以确保当修正了极点和增益中的相应一个时，错误样本中的明确的变化方向。
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64.发明授权公开(公告)号：US07977989B2
公开(公告)日：2011-07-12
申请号：US12730671
申请日：2010-03-24
IPC分类号： H03K5/12
CPC分类号： H03K5/02 , H03K5/06 , H03K19/017581 , H04L25/0288
摘要： Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.
摘要翻译： 公开了一种通过通信信道（例如，线，背板等）调整从发射机发射到接收机的信号的特性的电路。 该电路包括一个锁存器，该锁存器在阈值电压施加到锁存器之后多次接收电路中预定点处的信号并对信号的电压进行多次采样。 该电路还包括一个处理器，当采样电压指示转换点时，确定信号的特性，并且当采样电压不指示转换点时调整阈值电压。 当信号的特性在预定范围之外时，处理器通过调节发射机的电流和电压中的至少一个来调整信号的特性。
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公开(公告)号：US20100237915A1
公开(公告)日：2010-09-23
申请号：US12789544
申请日：2010-05-28
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the deter wined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译： 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 电压控制延迟环可以使用阻尼控制信号启动。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。
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66.发明授权公开(公告)号：US07791368B2
公开(公告)日：2010-09-07
申请号：US12012733
申请日：2008-02-05
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H02J1/06
摘要： Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply. The circuit includes a PVT detector configured to generate a control signal and an adjustable resistance device configured to adjust its resistance in response to the control signal.
摘要翻译： 公开了一种用于通过电源调节提供给IC的电压的电路。 电路包括被配置为产生控制信号的PVT检测器和被配置为响应于控制信号调整其电阻的可调电阻器件。
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67.发明授权Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization 有权用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置公开(公告)号：US07649933B2
公开(公告)日：2010-01-19
申请号：US11414522
申请日：2006-04-28
申请人： Christopher J. Abel , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Christopher J. Abel , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
CPC分类号： H04L25/062 , H04L25/03057
摘要： Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.
摘要翻译： 提供了用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置。 通过获得与信号相关联的数据眼睛的多个采样来确定偏移锁存器的位置，数据眼睛包括用于从给定二进制状态转换的多个轨迹; 基于样本确定至少两个轨迹的振幅; 以及基于所确定的振幅来确定偏移锁存器的位置。 偏移锁存器的初始位置例如可以放置在至少两个轨迹的确定幅度的中间。 偏移锁存器的初始位置可以可选地倾斜预定义的量以改善噪声容限。
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68.发明申请ANALOG AMPLIFIER HAVING DC OFFSET CANCELLATION CIRCUIT AND METHOD OF OFFSET CANCELLATION FOR ANALOG AMPLIFIERS 有权具有直流偏移消除电路的模拟放大器和模拟放大器偏移消除方法公开(公告)号：US20090212856A1
公开(公告)日：2009-08-27
申请号：US12437860
申请日：2009-05-08
IPC分类号： H03F1/02
CPC分类号： H03F3/45973 , H03F3/45977 , H03F2203/45101 , H03F2203/45434 , H03F2203/45564 , H03F2203/45588 , H03F2203/45622
摘要： An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier
摘要翻译： 具有DC偏移补偿的放大器包括至少一个输入节点和一对差分输出节点，偏置电路耦合到输入节点; 和多个电流源。 所选择的所述电流源耦合到输入节点以调整输入节点处的DC电压，以为放大器提供DC偏移补偿
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69.发明授权Methods and apparatus for interfacing a plurality of encoded serial data streams to a serializer/deserializer circuit 有权用于将多个编码的串行数据流连接到串行器/解串行器电路的方法和装置公开(公告)号：US07492291B2
公开(公告)日：2009-02-17
申请号：US11741789
申请日：2007-04-30
申请人： Brian Murray , Jacobo Riesco , Gregory W. Sheets , Lane A. Smith
发明人： Brian Murray , Jacobo Riesco , Gregory W. Sheets , Lane A. Smith
IPC分类号： H03M9/00
CPC分类号： H04L25/4908 , H03M5/145 , H04L25/03866 , H04L49/351
摘要： Methods and apparatus are provided for interfacing a plurality of encoded serial data streams, such as Serial Gigabit Media Independent Interface streams, to a serializer/deserializer circuit. A plurality of encoded serial data streams are transmitted by receiving the plurality of encoded serial data streams that have been encoded using an encoding scheme that provides a substantially uniform distribution of a first code and a second code; marking at least one of the encoded serial data streams (such as changing a first code to a predefined code); and combining at least two of the plurality of encoded serial data streams into a single data stream. A plurality of encoded serial data streams are received by receiving a single data stream comprised of the plurality of encoded serial data streams; detecting a mark in the single data stream; demultiplexing the single data stream into the plurality of encoded serial data streams based on the mark; and providing the demultiplexed plurality of encoded serial data streams to a decoder that decodes the plurality of encoded serial data streams using a decoding scheme that provides a substantially uniform distribution of a first code and a second code.
摘要翻译： 提供了用于将多个编码的串行数据流（诸如串行千兆位媒体独立接口流）连接到串行器/解串行器电路的方法和装置。 通过接收已经使用提供第一代码和第二代码的基本均匀分布的编码方案来编码的多个编码串行数据流来发送多个编码串行数据流; 标记编码串行数据流中的至少一个（例如将第一代码改变为预定义的代码）; 以及将所述多个编码串行数据流中的至少两个组合成单个数据流。 通过接收由多个编码串行数据流组成的单个数据流来接收多个编码串行数据流; 检测单个数据流中的标记; 基于标记将单个数据流解复用为多个编码串行数据流; 以及将解复用的多个编码的串行数据流提供给使用提供第一代码和第二代码的基本均匀分布的解码方案来解码多个经编码的串行数据流的解码器。
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70.发明申请Methods And Apparatus For Interfacing A Plurality Of Encoded Serial Data Streams To A Serializer/Deserializer Circuit 有权用于将多个编码串行数据流连接到串行器/解串器电路的方法和装置公开(公告)号：US20080095218A1
公开(公告)日：2008-04-24
申请号：US11741789
申请日：2007-04-30
申请人： Brian Murray , Jacobo Riesco , Gregory W. Sheets , Lane A. Smith
发明人： Brian Murray , Jacobo Riesco , Gregory W. Sheets , Lane A. Smith
IPC分类号： H04B1/00
CPC分类号： H04L25/4908 , H03M5/145 , H04L25/03866 , H04L49/351
摘要： Methods and apparatus are provided for interfacing a plurality of encoded serial data streams, such as Serial Gigabit Media Independent Interface streams, to a serializer/deserializer circuit. A plurality of encoded serial data streams are transmitted by receiving the plurality of encoded serial data streams that have been encoded using an encoding scheme that provides a substantially uniform distribution of a first code and a second code; marking at least one of the encoded serial data streams (such as changing a first code to a predefined code); and combining at least two of the plurality of encoded serial data streams into a single data stream. A plurality of encoded serial data streams are received by receiving a single data stream comprised of the plurality of encoded serial data streams; detecting a mark in the single data stream; demultiplexing the single data stream into the plurality of encoded serial data streams based on the mark; and providing the demultiplexed plurality of encoded serial data streams to a decoder that decodes the plurality of encoded serial data streams using a decoding scheme that provides a substantially uniform distribution of a first code and a second code.
摘要翻译： 提供了用于将多个编码的串行数据流（诸如串行千兆位媒体独立接口流）连接到串行器/解串行器电路的方法和装置。 通过接收已经使用提供第一代码和第二代码的基本均匀分布的编码方案来编码的多个编码串行数据流来发送多个编码串行数据流; 标记编码串行数据流中的至少一个（例如将第一代码改变为预定义的代码）; 以及将所述多个编码串行数据流中的至少两个组合成单个数据流。 通过接收由多个编码串行数据流组成的单个数据流来接收多个编码串行数据流; 检测单个数据流中的标记; 基于标记将单个数据流解复用为多个编码串行数据流; 以及将解复用的多个编码的串行数据流提供给使用提供第一代码和第二代码的基本均匀分布的解码方案来解码多个经编码的串行数据流的解码器。
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