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公开(公告)号：US20120033482A1
公开(公告)日：2012-02-09
申请号：US13274876
申请日：2011-10-17
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5685 , G11C13/0007 , G11C13/0026 , G11C13/0069
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。
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公开(公告)号：US08098513B2
公开(公告)日：2012-01-17
申请号：US13088610
申请日：2011-04-18
申请人： Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
发明人： Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
IPC分类号： G11C11/00
CPC分类号： G11C7/14 , G11C11/1673
摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。
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公开(公告)号：US08081504B2
公开(公告)日：2011-12-20
申请号：US12252170
申请日：2008-10-15
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Hongyue Liu , Hai Li
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Hongyue Liu , Hai Li
IPC分类号： G11C11/00
CPC分类号： G11C7/24 , G11C5/143 , G11C11/16 , G11C13/0002
摘要： Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations.
摘要翻译： 用于操作具有状态寄存器的存储器件的方法和装置。 在一些实施例中，存储器件具有由至少电阻式感测存储器组成的多个单独可编程的非易失性存储器单元。 在一些实施例中，存储器装置接合接口并维持状态寄存器，在数据传输操作期间至少记录错误或忙信号。
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64.发明申请公开(公告)号：US20110134682A1
公开(公告)日：2011-06-09
申请号：US13028246
申请日：2011-02-16
申请人： Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
发明人： Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0057
摘要： Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
摘要翻译： 公开了用于电阻随机存取存储器（RRAM）的可变写和读方法。 这些方法包括初始化写入序列并验证RRAM单元的电阻状态。 如果需要写入脉冲，则通过RRAM单元施加两个或更多写入脉冲，以将期望的数据状态写入RRAM单元。 每个后续写入脉冲具有基本上相同或更大的写入脉冲持续时间。 随后的写入脉冲被施加到RRAM单元，直到RRAM单元处于期望的数据状态，或直到预定数量的写入脉冲已经被施加到RRAM单元为止。 还公开了一种读取方法，其中随后的读取脉冲通过RRAM单元被施加，直到读取成功或直到预定数量的读取脉冲已经被应用于RRAM单元为止。
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公开(公告)号：US07952917B2
公开(公告)日：2011-05-31
申请号：US12794009
申请日：2010-06-04
申请人： Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
发明人： Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0057
摘要： Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
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公开(公告)号：US07944731B2
公开(公告)日：2011-05-17
申请号：US12904653
申请日：2010-10-14
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
摘要翻译： 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。
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公开(公告)号：US07936580B2
公开(公告)日：2011-05-03
申请号：US12254414
申请日：2008-10-20
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.
摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。
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公开(公告)号：US07826255B2
公开(公告)日：2010-11-02
申请号：US12210526
申请日：2008-09-15
申请人： Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
发明人： Haiwen Xi , Hongyue Liu , Xiaobin Wang , Yong Lu , Yiran Chen , Yuankai Zheng , Dimitar V. Dimitrov , Dexin Wang , Hai Li
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0057
摘要： Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
摘要翻译： 公开了用于电阻随机存取存储器（RRAM）的可变写和读方法。 这些方法包括初始化写入序列并验证RRAM单元的电阻状态。 如果需要写入脉冲，则通过RRAM单元施加两个或更多写入脉冲，以将期望的数据状态写入RRAM单元。 每个后续写入脉冲具有基本上相同或更大的写入脉冲持续时间。 随后的写入脉冲被施加到RRAM单元，直到RRAM单元处于期望的数据状态，或直到预定数量的写入脉冲已经被施加到RRAM单元为止。 还公开了一种读取方法，其中随后的读取脉冲通过RRAM单元被施加，直到读取成功或直到预定数量的读取脉冲已经被应用于RRAM单元为止。
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公开(公告)号：US20100097852A1
公开(公告)日：2010-04-22
申请号：US12254414
申请日：2008-10-20
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.
摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。
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公开(公告)号：US20100067282A1
公开(公告)日：2010-03-18
申请号：US12212798
申请日：2008-09-18
申请人： Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
发明人： Hongyue Liu , Yong Lu , Andrew Carter , Yiran Chen , Hai Li
CPC分类号： G11C7/14 , G11C11/1673
摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。
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