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61.发明授权Apparatus and method for producing signal conveying circuit status information 有权产生信号传输电路状态信息的装置和方法公开(公告)号：US07782017B2
公开(公告)日：2010-08-24
申请号：US11582443
申请日：2006-10-18
摘要： Apparatus is configured for producing an output signal indicating an operating status of a monitored circuit. An input signal relating to the monitored circuit is received at an input node. A pulse train generator, coupled to the input node, is configured for generating a pulse train of a prescribed repetition rate at a duty cycle alternated between first and second duty cycle values at a prescribed frequency. The duty cycle and frequency are indicative of operating status of the monitored circuit.
摘要翻译： 设备被配置为产生指示所监视电路的操作状态的输出信号。 在输入节点处接收与被监控电路相关的输入信号。 耦合到输入节点的脉冲串发生器被配置为以规定频率在第一和第二占空比值之间交替的占空比产生规定重复频率的脉冲串。 占空比和频率表示监控电路的运行状态。
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公开(公告)号：US07642759B2
公开(公告)日：2010-01-05
申请号：US11827704
申请日：2007-07-13
申请人： Robert C. Dobkin
发明人： Robert C. Dobkin
CPC分类号： G05F1/46 , H02J1/10 , Y10S323/907 , Y10T307/565
摘要： Circuits and methods for paralleling voltage regulators are provided. Improved current sharing and regulation characteristics are obtained by coupling control terminals of the voltage regulators together which results in precise output voltages and proportional current production. Distributing current generation among multiple paralleled voltage regulators improves heat dissipation and thereby reduces the likelihood that the current produced by the voltage regulators will be temperature limited.
摘要翻译： 提供了并联稳压器的电路和方法。 通过将电压调节器的控制端子耦合在一起来获得改善的电流共享和调节特性，这导致精确的输出电压和成比例的电流产生。 在多个并联稳压器之间分配电流产生器可改善散热，从而降低由稳压器产生的电流将受到温度限制的可能性。
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63.发明申请公开(公告)号：US20080272844A1
公开(公告)日：2008-11-06
申请号：US12174102
申请日：2008-07-16
CPC分类号： H03F1/483 , H03F3/3022 , H03F3/45192 , H03F2200/36 , H03F2200/513 , H03F2203/30033 , H03F2203/45302 , H03F2203/45512
摘要： A class AB folded-cascode amplifier having improved gain-bandwidth product, comprises a differential input circuit including a differential transistor pair coupled to a source of tail current and responsive to a differential input signal for conducting a first current, a cascode circuit coupled to the differential input circuit for supplying a second current thereto, and a class AB output stage. A compensation circuit is configured for feeding back mutually complementary compensation signals from an output node to the differential input circuit. Another compensation circuit is configured for feeding back a signal from the output of the output stage to the input of the output stage.
摘要翻译： 具有改进的增益带宽乘积的AB类折叠共源共栅放大器包括差分输入电路，差分输入电路包括耦合到尾电流源的差分晶体管对，并响应用于传导第一电流的差分输入信号，耦合到 用于提供第二电流的差分输入电路和AB类输出级。 补偿电路被配置为将相互补偿的补偿信号从输出节点反馈到差分输入电路。 另一个补偿电路被配置为将信号从输出级的输出反馈到输出级的输入端。
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64.发明授权
公开(公告)号：US5731731A
公开(公告)日：1998-03-24
申请号：US786500
申请日：1997-01-21
IPC分类号： H02M3/155 , H02M3/158 , H03K17/693
CPC分类号： H02M3/158 , H02M2001/0032 , Y02B70/16
摘要： Switching regulator circuits and methods are provided in which the output circuit is adaptable to maintain high efficiency over various load current levels. The regulator circuits generate one or more control signals in response to the load current and selectively route a switch driver control signal to one or more switches in the output circuit. The switches differ in their size, such that the most efficient switch can be used at a particular load current level. At low load current levels, the driver control signal is routed to output circuitry with smaller switch devices, which incur smaller driver current losses for a given frequency of operation, thereby increasing the regulator efficiency. At high load current levels, the driver control signal is routed to large switch devices, which incur greater driver current losses for a given frequency of operation, but which have a lower impedance. The regulator thus maintains high efficiency over a wide range of load currents while operating at a constant frequency.
摘要翻译： 提供了开关调节器电路和方法，其中输出电路适用于在各种负载电流水平上保持高效率。 调节器电路响应于负载电流产生一个或多个控制信号，并且选择性地将开关驱动器控制信号路由到输出电路中的一个或多个开关。 这些开关的尺寸不同，使得最高效的开关可以在特定负载电流水平下使用。 在低负载电流电平下，驱动器控制信号被路由到具有较小开关器件的输出电路，这对于给定的操作频率会产生更小的驱动器电流损耗，从而提高了调节器的效率。 在高负载电流水平下，驱动器控制信号被路由到大型开关器件，这对于给定的工作频率而言具有更大的驱动电流损耗，但具有较低的阻抗。 因此，在恒定频率下工作时，稳压器在宽范围的负载电流下保持高效率。
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65.发明授权Process for manufacturing a lead frame capacitor and capacitively-coupled isolator circuit using same 失效用于制造引线框电容器和使用其的电容耦合隔离电路的工艺
公开(公告)号：US5650357A
公开(公告)日：1997-07-22
申请号：US401033
申请日：1995-03-08
申请人： Robert C. Dobkin , Robert L. Reay
发明人： Robert C. Dobkin , Robert L. Reay
IPC分类号： H01L23/50 , H01L21/822 , H01L23/495 , H01L23/64 , H01L25/00 , H01L27/04 , H05K1/16 , H05K3/20 , H01L21/56 , H01L21/58 , H01L21/60 , H01L21/71
CPC分类号： H01L23/49575 , H01L23/49589 , H01L23/642 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/14 , H01L2924/19041 , H05K1/162 , H05K3/202 , Y10S257/904 , Y10T29/435
摘要： A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.
摘要翻译： 提供一种电容器，包括由常规集成电路封装中使用的引线框架结构的部分形成的第一和第二电极。 电极用介电模塑材料封装，其在电极之间提供介电绝缘。 还提供了一种低功率电容耦合数字隔离电路。 该电路采用本发明的一对引线框电容器，并包括差分驱动器和接收器电路。 接收机还可以包括可选的滤波器，以增加噪声和毛刺抗扰度。
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公开(公告)号：US5589709A
公开(公告)日：1996-12-31
申请号：US401027
申请日：1995-03-08
申请人： Robert C. Dobkin , Robert L. Reay
发明人： Robert C. Dobkin , Robert L. Reay
IPC分类号： H01L23/50 , H01L21/822 , H01L23/495 , H01L23/64 , H01L25/00 , H01L27/04 , H05K1/16 , H05K3/20
CPC分类号： H01L23/49575 , H01L23/49589 , H01L23/642 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/14 , H01L2924/19041 , H05K1/162 , H05K3/202 , Y10S257/904 , Y10T29/435
摘要： A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.
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67.再颁专利High speed junction field effect transistor for use in bipolar integrated circuits 失效用于双极型集成电路的高速结型场效应晶体管
公开(公告)号：USRE34821E
公开(公告)日：1995-01-03
申请号：US36935
申请日：1993-03-25
IPC分类号： H01L21/337 , H01L29/10 , H01L29/45 , H01L29/808 , H01L29/80 , H01L23/48 , H01L29/04
CPC分类号： H01L29/1066 , H01L29/456 , H01L29/66901 , H01L29/808
摘要： A high speed BIFET junction field effect transistor is formed in an epitaxial layer of one conductivity type and includes source and drain regions of opposite conductivity type interconnected by a thin channel region of the opposite conductivity type. A thin surface layer of the one conductivity type is formed over the channel region, and a highly conductive contact is formed on the surface layer intermediate the source and drain regions. The surface contact can comprise highly doped polycrystalline silicon material with a metal layer on the surface thereof. The surface contact and the epitaxial layer underlying the channel region comprise gates for the field effect transistor. Increased speed of operation comes from the increased conductivity of the surface contact.
摘要翻译： 高速BIFET结场效应晶体管形成在一种导电类型的外延层中，并且包括由相反导电类型的薄沟道区互连的相反导电类型的源区和漏区。 在沟道区域上形成一种导电类型的薄表面层，并且在源极和漏极区域之间的表面层上形成高导电性接触。 表面接触可以包括在其表面上具有金属层的高掺杂多晶硅材料。 沟道区下面的表面接触和外延层包括用于场效应晶体管的栅极。 增加的操作速度来自表面接触的增加的电导率。
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公开(公告)号：US5334928A
公开(公告)日：1994-08-02
申请号：US98461
申请日：1993-07-27
摘要： A three terminal control circuit for a low dropout voltage regulator having a PNP pass transistor is provided. The control circuit is capable of pulling the base drive point down to a voltage of 3.0 volts or less to permit a current limiting resistor to be inserted between the base drive point and the base of the PNP pass transistor. The control circuit includes a pair of small-valued capacitors for providing stable operation with different output capacitors. The control circuit can also be used with p-channel FET pass transistors.
摘要翻译： 提供一种具有PNP传输晶体管的低压差稳压器的三端控制电路。 控制电路能够将基极驱动点拉低至3.0伏或更小的电压，以允许限流电阻器插入在PNP传输晶体管的基极驱动点和基极之间。 该控制电路包括一对小值电容器，用于提供与不同输出电容器的稳定操作。 控制电路也可以与p沟道FET传输晶体管一起使用。
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公开(公告)号：US5128631A
公开(公告)日：1992-07-07
申请号：US652053
申请日：1991-02-06
申请人： George F. Feliz , Robert C. Dobkin
发明人： George F. Feliz , Robert C. Dobkin
CPC分类号： H03F1/0261 , H03F3/3076
摘要： An operational amplifier having input and output stages with positive capacitive feedback to the output stage derived from a point in the circuit where the voltage is proportional to the output voltage.
摘要翻译： 具有输入和输出级的运算放大器，其具有从电压与输出电压成比例的电路中的点导出到输出级的正电容反馈。
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公开(公告)号：US5070259A
公开(公告)日：1991-12-03
申请号：US456354
申请日：1989-12-26
IPC分类号： H03K19/003
CPC分类号： H03K19/00384
摘要： A constant current amplifier stage for a voltage comparator circuit includes a first CMOS transistor pair having a common gate terminal and a common drain terminal and a second CMOS transistor pair which functions as a load for the first CMOS transistor pair. The second CMOS transistor pair has a common gate terminal and a common drain terminal both of which are connected to the common drain terminal of the first CMOS transistor pair. The transistors are configured so that the current through the first transistor pair at null is at least twice the current through the second transistor pair at null voltage.
摘要翻译： 用于电压比较器电路的恒流放大器级包括具有公共栅极端子和公共漏极端子的第一CMOS晶体管对和用作第一CMOS晶体管对的负载的第二CMOS晶体管对。 第二CMOS晶体管对具有公共栅极端子和公共漏极端子，它们均连接到第一CMOS晶体管对的公共漏极端子。 晶体管被配置为使得在零点处通过第一晶体管对的电流在零电压下至少是通过第二晶体管对的电流的两倍。
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