摘要:
A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′1, . . . , v′n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n′ column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.
摘要:
A variable focus lens has a housing (1) and an actuator (8) which are mutually displaceable along an optical axis (A) of the lens. A primary membrane (15) is arranged between a first chamber (24, 26) and a second chamber (30, 32), with the first and second chambers being filled with liquids of similar density but different indices of refraction. First and second auxiliary membranes (19, 17) are provided for volume compensation. The first auxiliary membrane (19) forms a wall section of the first chamber (24, 26), and the second auxiliary membrane (17) forms a wall section of the second chamber (30, 32), at least one or both of the auxiliary membranes facing environmental air at its outer side.
摘要:
A device includes a non-volatile memory and a control unit, wherein the control unit is configured to change over programming of data of the non-volatile memory from a first programming mode to a second, different programming mode based on the occurrence of a control signal.
摘要:
An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word.
摘要:
A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v′)) based on a coded binary word (v′). The error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v′)), if the error syndrome bit sequence (s(v′)) indicates that the coded binary word (v′) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)′)—caused by the test bit sequence (Ti)—of the circuit.
摘要:
An optical apparatus includes a housing, a deformable lens, and a lens shaper. The lens shaper defines the shape of the deformable lens. A first mechanism is positioned within the housing to adjust an optical property of the deformable lens. A second mechanism is positioned within the housing to adjust an optical property of the deformable lens. The second mechanism is at least one of an electromechanical actuator or motor. The first mechanism and the second mechanism are different types of mechanisms.
摘要:
The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.
摘要:
The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.
摘要:
The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.
摘要:
Some embodiments of the present disclosure relate to regulators for charge pumps. Such regulators selectively activate a charge pump based not only on the voltage output of the charge pump, but also on an series of wake-up pulses that are delivered at predetermined time intervals and which are delivered independently of the voltage output of the charge pump. Hence, these wake-up pulses prevent extended periods of time in which the charge pump is inactive, thereby helping to prevent latch-up in some situations.