公开(公告)号：US20230299727A1

公开(公告)日：2023-09-21

申请号：US18186915

申请日：2023-03-20

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F3/195 ,  H03F1/02 ,  H03H11/28 ,  H04B1/16 ,  H03H7/38 ,  H03F1/22 ,  H03F1/56 ,  H03F3/193 ,  H03F3/72 ,  H04B1/00

CPC classification number: H03F3/195 ,  H03F1/0205 ,  H03H11/28 ,  H04B1/16 ,  H03H7/38 ,  H03F1/0261 ,  H03F1/223 ,  H03F1/565 ,  H03F3/193 ,  H03F3/72 ,  H04B1/006 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/387 ,  H03F2200/111 ,  H03F2203/7209 ,  H03F2203/7236

Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

公开(公告)号：US11476813B2

公开(公告)日：2022-10-18

申请号：US16968024

申请日：2019-01-28

Applicant: pSemi Corporation

Inventor： Miles Sanner ,  Emre Ayranci

IPC: H03F3/72 ,  H03F1/22 ,  H03F3/195 ,  H03F3/21 ,  H03F1/56 ,  H03F3/193 ,  H03F3/16 ,  H03F1/02 ,  H04B1/16

Abstract: A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

公开(公告)号：US11152907B2

公开(公告)日：2021-10-19

申请号：US16860739

申请日：2020-04-28

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F3/193 ,  H03F1/32 ,  H03F3/72 ,  H03F1/22 ,  H03G3/30 ,  H03G1/00 ,  H03G3/00 ,  H03F3/21

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

公开(公告)号：US11005425B2

公开(公告)日：2021-05-11

申请号：US16677477

申请日：2019-11-07

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F3/72 ,  H03F1/02 ,  H03F1/08 ,  H03F3/195 ,  H03F1/56 ,  H03F3/193

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

公开(公告)号：US10951252B2

公开(公告)日：2021-03-16

申请号：US16242870

申请日：2019-01-08

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner ,  Phanindra Yerramilli

IPC: H04B1/06 ,  H03F3/195 ,  H04B1/18 ,  H03F1/26 ,  H04B1/04 ,  H04B1/00

Abstract: Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.

公开(公告)号：US20200343862A1

公开(公告)日：2020-10-29

申请号：US15931236

申请日：2020-05-13

Applicant: pSemi Corporation

Inventor： Kashish Pal ,  Emre Ayranci ,  Miles Sanner

IPC: H03F1/22 ,  H03F3/193 ,  H03F1/26 ,  H04L27/26 ,  H03F3/68

Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

公开(公告)号：US20200266778A1

公开(公告)日：2020-08-20

申请号：US16279487

申请日：2019-02-19

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner ,  Phanindra Yerramilli

IPC: H03F3/30 ,  H03F3/45 ,  H03F3/16

Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.

公开(公告)号：US20200220508A1

公开(公告)日：2020-07-09

申请号：US16242883

申请日：2019-01-08

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner ,  Phanindra Yerramilli

IPC: H03F3/195 ,  H03F1/56 ,  H04B1/16

Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.

公开(公告)号：US10673401B2

公开(公告)日：2020-06-02

申请号：US16046962

申请日：2018-07-26

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03G3/30 ,  H03F3/193 ,  H03F1/32 ,  H03F1/22 ,  H03F3/72 ,  H03G1/00 ,  H03G3/00 ,  H03F3/21

Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

公开(公告)号：US20200127618A1

公开(公告)日：2020-04-23

申请号：US16664646

申请日：2019-10-25

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F3/195 ,  H03F3/72 ,  H03F3/193 ,  H03F1/56 ,  H03F1/22 ,  H03F1/02 ,  H03H7/38 ,  H04B1/16 ,  H03H11/28 ,  H04B1/00

Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.