-
公开(公告)号:US20240364269A1
公开(公告)日:2024-10-31
申请号:US18653486
申请日:2024-05-02
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner
CPC classification number: H03F1/0277 , H03F1/086 , H03F1/565 , H03F3/193 , H03F3/195 , H03F3/72 , H03F2200/111 , H03F2200/18 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/252 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/321 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/411 , H03F2200/42 , H03F2200/429 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03F2203/7206 , H03F2203/7209 , H03F2203/7233
Abstract: A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.
-
公开(公告)号:US12101065B2
公开(公告)日:2024-09-24
申请号:US18492544
申请日:2023-10-23
Applicant: pSemi Corporation
Inventor: Miles Sanner , Emre Ayranci , Parvez Daruwalla
CPC classification number: H03F1/223 , H03F3/193 , H03F3/21 , H03F2200/294 , H03F2203/7236
Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
-
公开(公告)号:US20240243706A1
公开(公告)日:2024-07-18
申请号:US18620994
申请日:2024-03-28
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner
IPC: H03F3/195 , H03F1/02 , H03F1/22 , H03F1/56 , H03F3/193 , H03F3/72 , H03H7/38 , H03H11/28 , H04B1/00 , H04B1/16
CPC classification number: H03F3/195 , H03F1/0205 , H03F1/0261 , H03F1/223 , H03F1/565 , H03F3/193 , H03F3/72 , H03H7/38 , H03H11/28 , H04B1/006 , H04B1/16 , H03F2200/111 , H03F2200/294 , H03F2200/387 , H03F2200/451 , H03F2203/7209 , H03F2203/7236
Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
-
公开(公告)号:US11967935B2
公开(公告)日:2024-04-23
申请号:US17240852
申请日:2021-04-26
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Phanindra Yerramilli
CPC classification number: H03F1/26 , H03F1/223 , H03F3/195 , H03F2200/294 , H03F2200/372 , H03F2200/451 , H03G3/344
Abstract: Methods and systems for a multi gain LNA architecture achieving minimum phase discontinuity between all the different active and passive gain modes that uses different LNA configurations and settings for single and multi-stage LNAs by a configurable combined output matching and phase adjusting circuitry.
-
公开(公告)号:US20240007059A1
公开(公告)日:2024-01-04
申请号:US17855418
申请日:2022-06-30
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Jubaid Qayyum , Phanindra Yerramilli , Miles Sanner
CPC classification number: H03F1/565 , H03F3/195 , H03F2200/451 , H03F2200/294 , H03F2200/222 , H03F2200/387
Abstract: Circuits and methods for an LNA that enable selection of a first mode providing high gain with wide output impedance matching, and a second mode providing wideband output impedance matching with improved NF and linearity at moderate gain. Some embodiments allow multiple intermediate modes to enable selection of gain versus linearity and NF. One embodiment includes a matching network having an input terminal configured to be coupled to an amplified-signal terminal of an amplification core, and an output terminal, the matching network including a first inductor coupled between the input terminal and a first node; a second inductor coupled to the first node; a boosted amplification branch coupled between the input terminal and the output terminal; and a non-amplification branch coupled between the first node and the output terminal; wherein the boosted amplification branch is enabled in a first mode, and the non-amplification branch is enabled in a second mode.
-
公开(公告)号:US11831280B2
公开(公告)日:2023-11-28
申请号:US18168346
申请日:2023-02-13
Applicant: pSemi Corporation
Inventor: Miles Sanner , Emre Ayranci , Parvez Daruwalla
CPC classification number: H03F1/223 , H03F3/193 , H03F3/21 , H03F2200/294 , H03F2203/7236
Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
-
公开(公告)号:US11728837B2
公开(公告)日:2023-08-15
申请号:US17366614
申请日:2021-07-02
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Phanindra Yerramilli
CPC classification number: H04B1/18 , H03F1/26 , H03F3/195 , H04B1/0057 , H04B1/0458 , H03F2200/294 , H03F2200/451
Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
-
公开(公告)号:US11611319B2
公开(公告)日:2023-03-21
申请号:US16953141
申请日:2020-11-19
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner
IPC: H03F1/22 , H03F3/195 , H03F1/02 , H03H11/28 , H04B1/16 , H03H7/38 , H03F1/56 , H03F3/193 , H03F3/72 , H04B1/00
Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
-
公开(公告)号:US11251765B2
公开(公告)日:2022-02-15
申请号:US16852275
申请日:2020-04-17
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Ke Li , James Francis McElwee , Tero Tapio Ranta , Kevin Roberts , Chih-Chieh Cheng
IPC: H04B1/04 , H04B1/40 , H01B1/00 , H04W88/06 , H03H7/38 , H03H7/01 , H04B1/00 , H04W72/04 , H04W28/06 , H04L5/00
Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability. In a third version, CA direct mapped adaptive tuning networks include filter tuning blocks for selected lower frequency bands.
-
公开(公告)号:US10771025B1
公开(公告)日:2020-09-08
申请号:US16279487
申请日:2019-02-19
Applicant: pSemi Corporation
Inventor: Emre Ayranci , Miles Sanner , Phanindra Yerramilli
Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
-
-
-
-
-
-
-
-
-