DEFINITION OF WAKEUP BUS MESSAGES FOR PARTIAL NETWORKING
    61.
    发明申请
    DEFINITION OF WAKEUP BUS MESSAGES FOR PARTIAL NETWORKING 有权
    用于部分网络的唤醒总线消息的定义

    公开(公告)号:US20120271975A1

    公开(公告)日:2012-10-25

    申请号:US13518139

    申请日:2010-12-20

    IPC分类号: G06F13/42

    摘要: A method of encoding a digital bus message information, in particular a wake-up bus message information or configuring data, on a bus system, the method comprising: encoding a predetermined part of digital bus message information bits by means of sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases that corresponds to a value of the predetermined part. A respective digital bus message, particularly for use on a bus system, is to be encoded in accordance with the method.Further, a bus node for a system bus having a plurality of stations that are coupled together by means of an arrangement of bus lines, comprises decoding circuitry configured for an analysis of sub-patterns in a stream of data on at least one bus line, and analysing circuitry configured to detect encoded digital bus message information, in particular a wake-up bus message information or configuring data, transmitted in a stream of line symbols on the bus system, wherein the digital bus message information is encoded in accordance with the method.

    摘要翻译: 一种在总线系统上编码数字总线消息信息,特别是唤醒总线消息信息或配置数据的方法,所述方法包括:通过子模式对预定部分的数字总线消息信息位进行编码 在至少一条总线上的线符号流,其中子模式由连续的显性和隐性相组成,包括隐性和主线符号,其中隐性相包括至少两个隐性线符号,以便建立比例 连续的显性和隐性相位对应于预定部分的值。 将根据该方法对相应的数字总线消息进行编码,特别是用于总线系统的数字总线消息。 此外,用于具有通过总线线路布置而耦合在一起的多个站的系统总线的总线节点包括被配置用于分析至少一条总线上的数据流中的子模式的解码电路, 以及分析电路,被配置为检测在总线系统上的线符号流中发送的编码数字总线消息信息,特别是唤醒总线消息信息或配置数据,其中数字总线消息信息根据该方法 。

    Multiprocessor gateway
    62.
    发明授权
    Multiprocessor gateway 有权
    多处理器网关

    公开(公告)号:US08171199B2

    公开(公告)日:2012-05-01

    申请号:US12227261

    申请日:2007-04-17

    IPC分类号: G06F13/00

    摘要: A multiprocessor gateway for multiple serial buses includes: multiple communication modules that are each provided for connection of one serial bus; multiple processors for processing data that are transferred in word-based fashion, via an internal system bus appurtenant to the respective processor, between the processor and the communication modules, the internal system buses of the multiprocessor gateway being connected to the communication modules, which have a respective appurtenant interface unit for each system bus, each processor exchanging data, via its appurtenant system bus and the interface unit, appurtenant to the system bus, of a communication module, with the serial bus connected to the communication module, independently of the other processors and without waiting time.

    摘要翻译: 用于多个串行总线的多处理器网关包括:多个通信模块,每个通信模块被提供用于连接一个串行总线; 用于处理以基于字的方式传送的数据的多个处理器,通过附属于相应处理器的内部系统总线,处理器和通信模块之间,多处理器网关的内部系统总线连接到通信模块, 用于每个系统总线的相应附属接口单元,每个处理器通过其附属系统总线和与系统总线相连的通信模块的接口单元交换数据,其中串行总线与通信模块连接,独立于其他 处理器,无需等待时间。

    CIRCUIT CONFIGURATION HAVING A TRANSCEIVER CIRCUIT FOR A BUS SYSTEM AND NODES FOR A BUS SYSTEM
    63.
    发明申请
    CIRCUIT CONFIGURATION HAVING A TRANSCEIVER CIRCUIT FOR A BUS SYSTEM AND NODES FOR A BUS SYSTEM 有权
    具有用于总线系统的收发电路的电路配置和用于总线系统的节点

    公开(公告)号:US20110271130A1

    公开(公告)日:2011-11-03

    申请号:US12998575

    申请日:2009-09-25

    IPC分类号: G06F1/32

    摘要: A circuit configuration for a node of a bus system includes a transceiver circuit and a control circuit connected to the transceiver circuit. The transceiver circuit has an idle mode, in which it has a reduced power consumption in comparison with at least one operating mode, and the transceiver circuit is supplied with power in the at least one operating mode via a power supply unit integrated into the transceiver circuit. The control circuit is connected to the power supply unit to supply the control circuit with power in the idle mode, and the circuit configuration has a controllable voltage regulator which is coupled to the transceiver circuit in such a way that the voltage regulator is deactivated in the idle mode to reduce the power consumption and activated in the operating mode to supply power to the transceiver circuit and the control circuit.

    摘要翻译: 总线系统的节点的电路配置包括收发器电路和连接到收发器电路的控制电路。 收发器电路具有空闲模式,其中与至少一个操作模式相比具有降低的功耗,并且收发器电路经由集成到收发器电路中的电源单元在至少一个操作模式中被供电 。 控制电路连接到电源单元以向控制电路提供处于空闲模式的电力,并且电路配置具有可控制的电压调节器,其以收发器电路耦合,使得电压调节器在 空闲模式以降低功耗并在操作模式下激活以向收发器电路和控制电路供电。

    NETWORK MODE SWITCHING METHOD AND SERIAL DATA COMMUNICATION NETWORK
    64.
    发明申请
    NETWORK MODE SWITCHING METHOD AND SERIAL DATA COMMUNICATION NETWORK 有权
    网络模式切换方法和串行数据通信网络

    公开(公告)号:US20110194458A1

    公开(公告)日:2011-08-11

    申请号:US12975097

    申请日:2010-12-21

    IPC分类号: H04L12/28

    摘要: Disclosed is a method of switching modes in a serial data communication network comprising a plurality of interconnected nodes, each of said nodes comprising a plurality of mode-dependent configurations, the method including, during a first mode, issuing an instruction to said nodes, said instruction identifying a next mode of the data communication network; terminating said first mode; and following said termination, reconfiguring each of said nodes in accordance with the configuration corresponding to said next mode identified by said instruction. A serial data communication network implementing such a method is also disclosed.

    摘要翻译: 公开了一种在包括多个互连节点的串行数据通信网络中切换模式的方法,每个所述节点包括多个依赖于模式的配置,所述方法包括在第一模式期间向所述节点发出指令,所述方法包括: 识别数据通信网络的下一个模式的指令; 终止所述第一模式; 并且在所述终止之后,根据与由所述指令识别的所述下一个模式对应的配置重新配置所述节点。 还公开了实现这种方法的串行数据通信网络。

    VEHICLE GATEWAY, AND APPARATUS AND METHOD FOR VEHICLE NETWORK INTERFACE
    65.
    发明申请
    VEHICLE GATEWAY, AND APPARATUS AND METHOD FOR VEHICLE NETWORK INTERFACE 审中-公开
    车辆网关,以及用于车辆网络接口的装置和方法

    公开(公告)号:US20110144858A1

    公开(公告)日:2011-06-16

    申请号:US13058102

    申请日:2008-10-17

    IPC分类号: H04W40/00 G06F7/00 H04W36/00

    摘要: Provide are a vehicle gateway, and an apparatus and a method for vehicle network interface. The vehicle gateway includes a first interface connected to each unit of a vehicle network, a second interface connected to one or more access devices acquiring vehicle information from the vehicle network, and a packet processor connecting the first interface to the second interface, and determining a communication system and a communication path to each of the access devices and a process order of the vehicle information acquisition.

    摘要翻译: 提供车辆网关,车辆网络接口的装置和方法。 车辆网关包括连接到车辆网络的每个单元的第一接口,连接到从车辆网络获取车辆信息的一个或多个接入设备的第二接口,以及将第一接口连接到第二接口的分组处理器, 通信系统和到每个接入设备的通信路径以及车辆信息获取的处理顺序。

    Gateway for automatically routing messages between buses
    67.
    发明授权
    Gateway for automatically routing messages between buses 有权
    在总线之间自动路由消息的网关

    公开(公告)号:US07907623B2

    公开(公告)日:2011-03-15

    申请号:US12279463

    申请日:2007-02-07

    IPC分类号: H04L12/28 H04L12/56 G01M17/00

    摘要: A gateway is provided for automatically routing messages between buses, the gateway being connected to multiple communication components for temporarily storing and transmitting messages via these buses, and having a gateway control unit which is connected to the communication components via a system bus for the exchange of messages, and which receives notification from each communication component of the occurrence therein of a message to be routed as an external event. The gateway control unit has a vector memory which includes a first memory region for storing communication component vectors, a communication component vector being provided for each message group of a communication component, and the vector indicating the point in time of the next expected internal event for a message that is temporarily stored in the communication component, and indicating a vector jump address to a message vector which is stored in a second memory region of the vector memory.

    摘要翻译: 提供了一种用于在总线之间自动路由消息的网关,网关连接到多个通信组件,用于经由这些总线临时存储和发送消息,并且具有通过系统总线连接到通信组件的网关控制单元,用于交换 消息,并且其从每个通信组件接收其中发生的消息作为外部事件被路由的消息。 网关控制单元具有向量存储器,其包括用于存储通信组件向量的第一存储区域,为通信组件的每个消息组提供的通信组件向量,以及指示下一预期内部事件的时间点的向量, 临时存储在通信部件中的消息,并且向向量存储器的第二存储区域中存储的消息向量指示向量跳转地址。

    METHOD FOR TRANSMITTING DATA IN A CYCLE-BASED COMMUNICATION SYSTEM
    68.
    发明申请
    METHOD FOR TRANSMITTING DATA IN A CYCLE-BASED COMMUNICATION SYSTEM 审中-公开
    用于在基于周期的通信系统中发送数据的方法

    公开(公告)号:US20110022752A1

    公开(公告)日:2011-01-27

    申请号:US12735136

    申请日:2008-12-10

    IPC分类号: G06F13/42 G06F13/00

    摘要: In a method for transmitting data from a transmitting user of a cycle-based communication system to a receiving user of the communication system, the data are transmitted via a communication medium in messages that repeat in communication cycles and that respectively include a plurality of data blocks. The receiving user identifies the end of the data blocks in the received messages and subsequently extracts the transmitted data from the identified data blocks.

    摘要翻译: 在从基于周期的通信系统的发送用户向通信系统的接收用户发送数据的方法中,在通信周期中重复的消息中经由通信介质发送数据,并且分别包括多个数据块 。 接收用户识别接收到的消息中的数据块的结束,并随后从识别的数据块中提取发送的数据。

    Method for transmitting a data transfer block and method and system for transferring a data transfer block
    69.
    发明申请
    Method for transmitting a data transfer block and method and system for transferring a data transfer block 有权
    用于发送数据传送块的方法以及用于传送数据传送块的方法和系统

    公开(公告)号:US20100293443A1

    公开(公告)日:2010-11-18

    申请号:US12308488

    申请日:2007-09-25

    申请人: Josef Newald

    发明人: Josef Newald

    IPC分类号: H03M13/09 G06F11/10

    摘要: A method for transmitting a data transfer block, the data transfer block comprising at least one data segment having a predetermined number of one or more data units, to be identified using validity information, and a header segment, the method including the following steps: a) writing a data unit into a first area of an output register predetermined for the data segment, from which the buffered data transfer block is transmitted via a bus system at a predetermined transmission instant with the aid of a time multiplexing method; b) writing a validity datum, implemented as a toggle bit or as an N-bit counter, into a second area of the output register predetermined for the header segment, the particular validity datum specifying the validity of the corresponding written data unit; c) enabling the data transfer block buffered in the output register for transmission, after the particular data unit and the corresponding validity datum are written into the output register; d) repeating steps (a) through (c) until the predetermined number of the data units and the corresponding validity data are written or the predetermined transmission instant is reached; and e) transmitting the enabled data transfer block buffered in the output register at the transmission instant.

    摘要翻译: 一种用于发送数据传输块的方法,所述数据传输块包括具有预定数量的一个或多个数据单元的至少一个数据段以使用有效性信息来标识,以及报头段,所述方法包括以下步骤: 将数据单元写入到为数据段预定的输出寄存器的第一区域中,借助于时间复用方法,经由总线系统经由总线系统从其传输预定的传输时间; b)将作为翻转位或作为N位计数器实现的有效性数据写入到为标题段预定的输出寄存器的第二区域中,该特定有效性数据指定对应的写入数据单元的有效性; c)在将特定数据单元和相应的有效性数据写入输出寄存器之后,启用缓冲在输出寄存器中的数据传输块进行传输; d)重复步骤(a)至(c),直到写入预定数量的数据单元和相应的有效数据或达到预定的传输时刻; 以及e)在传输时刻发送缓冲在输出寄存器中的使能数据传输块。