公开(公告)号：US4866701A

公开(公告)日：1989-09-12

申请号：US240745

申请日：1988-09-02

申请人： James N. Giacopelli ,  Walter D. Sincoskie

发明人： James N. Giacopelli ,  Walter D. Sincoskie

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/1561 ,  H04L49/255 ,  H04L49/258 ,  H04L2012/561 ,  H04L2012/5631 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5652

摘要： A novel packet switch architecture is disclosed. In the novel packet switch, inputs are dynamically allocated between newly arriving and recirculating packets to make maximum use of available bandwidth while simultaneously resolving output port conflicts.

摘要翻译： 公开了一种新颖的分组交换架构。 在新型分组交换机中，在新到达和再循环分组之间动态分配输入，以最大限度地利用可用带宽，同时解决输出端口冲突。

公开(公告)号：US4849968A

公开(公告)日：1989-07-18

申请号：US164020

申请日：1988-03-04

申请人： Jonathan S. Turner

发明人： Jonathan S. Turner

IPC分类号： H04Q11/04 ,  H04L12/18 ,  H04L12/54 ,  H04L12/56 ,  H04L12/58

CPC分类号： H04L49/505 ,  H04L12/1854 ,  H04L49/106 ,  H04L49/1561 ,  H04L49/201 ,  H04L49/203 ,  H04L2012/5652 ,  H04L49/1507 ,  H04L49/25 ,  H04L49/253 ,  H04L49/254 ,  H04L49/30 ,  H04L49/357 ,  H04L49/557

摘要： A Buffer Management System for a general multipoint packet switching network where the network has terminals transmitting data in the form of packets belonging to multiple channels over communication links through a packet switch array, the packet switches of the array receiving incoming packets from input data links and having memory arrays for temporarily storing the incoming packets for retransmitting the stored packets over output links. The Buffer Management System determines whether a packet should be stored, retransmitted, or discarded during an overload condition by identifying each incoming packet as either an excess packet or a nonexcess packet based on the number of packets stored in the memory array of the same channel as the incoming packet, and writing an incoming nonexcess packet into the memory array when the memory array is full and at least one excess packet is in the memory array and for discarding the excess packet from the memory array.

摘要翻译： 一种用于通用多点分组交换网络的缓冲器管理系统，其中网络具有通过分组交换阵列在通信链路上以属于多个信道的分组的形式发送数据的阵列，阵列的分组交换从输入数据链路接收传入的分组， 具有用于临时存储用于通过输出链路重传所存储的分组的输入分组的存储器阵列。 缓冲器管理系统通过基于存储在同一通道的存储器阵列中的分组数目将每个输入分组标识为过量分组或非过滤分组来确定在过载状态期间是否应该存储，重传或丢弃分组， 输入分组，并且当存储器阵列已满并且至少一个多余的分组在存储器阵列中并且用于从存储器阵列丢弃多余的分组时，将传入的无过滤分组写入存储器阵列。

公开(公告)号：US4734907A

公开(公告)日：1988-03-29

申请号：US773380

申请日：1985-09-06

申请人： Jonathan S. Turner

发明人： Jonathan S. Turner

IPC分类号： H04Q11/04 ,  H04L12/18 ,  H04L12/54 ,  H04L12/56 ,  H04L12/58 ,  H04J3/26

CPC分类号： H04L49/505 ,  H04L12/1854 ,  H04L49/106 ,  H04L49/1561 ,  H04L49/201 ,  H04L49/203 ,  H04L2012/5652 ,  H04L49/1507 ,  H04L49/25 ,  H04L49/253 ,  H04L49/254 ,  H04L49/30 ,  H04L49/357 ,  H04L49/557

摘要： A high performance packet switching network that can be used to provide voice data and video communication on a large scale is disclosed. The packet switching network has a broadcast capability which makes it suitable for applications including commercial television distribution and conferencing.The basic switching capability of the network is provided by a switching module which is capable of producing a desired number of copies of a broadcast packet and routing the copied packets to desired destinations. A plurality of switching modules may be interconnected to form a packet switch. Interconnection circuitry is provided so that the number of interconnected switch modules may be varied with a minimum of recabling.

摘要翻译： 公开了一种可用于大规模提供语音数据和视频通信的高性能分组交换网络。 分组交换网络具有广播能力，使其适用于包括商业电视分配和会议在内的应用。 网络的基本交换能力由切换模块提供，切换模块能够产生所需数量的广播分组的副本，并将复制的分组路由到期望的目的地。 多个交换模块可以互连以形成分组交换机。 提供了互连电路，使得互连的交换机模块的数量可以以最小的重新配置来改变。

公开(公告)号：US20110199925A1

公开(公告)日：2011-08-18

申请号：US13029171

申请日：2011-02-17

申请人： Masayuki SHINOHARA

发明人： Masayuki SHINOHARA

IPC分类号： H04L12/26

CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L49/1561 ,  H04L49/256 ,  H04L49/455

摘要： A packet switching equipment and a switch control system employing the same performs operation of the switch core portion independent of content of decision of an arbiter portion and overall equipment can be constructed with simple control structure. The packet switching equipment includes input buffer portions temporarily storing packets arriving to the input ports and outputting packets with adding labels indicative of destination port numbers, a switch core portion for switching the packets on the basis of labels added to the input buffer portions, and an arbiter portion adjusting input buffer portions to provide output permissions for outputting to the output ports. A sorting network autonomously sorting and concentrating the packets on the basis of the labels added to the packets is employed in the switch core portion.

摘要翻译： 分组交换设备和采用该分组交换设备的交换机控制系统可以独立于仲裁器部分的决策内容和总体设备来执行交换机核心部分的操作，可以用简单的控制结构来构造。 分组交换设备包括临时存储到达输入端口的分组的输入缓冲器部分，并且输出具有指示目的地端口号的添加标签的分组，用于基于添加到输入缓冲器部分的标签来切换分组的交换机核心部分，以及 仲裁器部分调节输入缓冲器部分以提供输出到输出端口的输出许可。 在交换机核心部分中采用基于添加到分组的标签来自动排序和集中分组的分类网络。

公开(公告)号：US07916724B2

公开(公告)日：2011-03-29

申请号：US12786487

申请日：2010-05-25

申请人： Masayuki Shinohara

发明人： Masayuki Shinohara

IPC分类号： H04L12/28

CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L49/1561 ,  H04L49/256 ,  H04L49/455

摘要： A packet switching equipment and a switch control system employing the same performs operation of the switch core portion independent of content of decision of an arbiter portion and overall equipment can be constructed with simple control structure. The packet switching equipment includes input buffer portions temporarily storing packets arriving to the input ports and outputting packets with adding labels indicative of destination port numbers, a switch core portion for switching the packets on the basis of labels added to the input buffer portions, and an arbiter portion adjusting input buffer portions to provide output permissions for outputting to the output ports. A sorting network autonomously sorting and concentrating the packets on the basis of the labels added to the packets is employed in the switch core portion.

摘要翻译： 分组交换设备和采用该分组交换设备的交换机控制系统可以独立于仲裁器部分的决策内容和总体设备来执行交换机核心部分的操作，可以用简单的控制结构来构造。 分组交换设备包括临时存储到达输入端口的分组的输入缓冲器部分，并且输出具有指示目的地端口号的添加标签的分组，用于基于添加到输入缓冲器部分的标签来切换分组的交换机核心部分，以及 仲裁器部分调节输入缓冲器部分以提供输出到输出端口的输出许可。 在交换机核心部分中采用基于添加到分组的标签来自动排序和集中分组的分类网络。

公开(公告)号：US07336612B1

公开(公告)日：2008-02-26

申请号：US09916406

申请日：2001-07-27

申请人： Saeeda Khankhel

发明人： Saeeda Khankhel

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/105 ,  H04L49/1561 ,  H04L2012/5642 ,  H04L2012/5651 ,  H04L2012/5681

摘要： The present invention is directed to a high performance broadband ATM switching system comprised of concentrator, non-recirculating sort-trap and queuing stages. The concentrator stage concentrates cells entering the switch by discarding idle inputs thereto. Cells arriving at the non-recirculating sort-trap stage during a time slot are sorted based upon destination address and priority. Cells having a unique address for the time slot are placed in a corresponding output queue while cells having non-unique destination addresses are re-routed to a trap buffer which ages the cell until a subsequent time slot in which the destination address is unique.

摘要翻译： 本发明涉及一种由集中器，非再循环排序和排队阶段组成的高性能宽带ATM交换系统。 集中器级通过丢弃进入开关的空闲电源来集中电池。 在时隙期间到达非再循环分类陷阱阶段的单元根据目的地址和优先级进行排序。 具有时隙的唯一地址的单元被放置在相应的输出队列中，而具有非唯一目的地地址的小区被重新路由到陷阱缓冲器，该陷阱缓冲器使该小区老化，直到目的地地址是唯一的后续时隙。

公开(公告)号：US20070110045A1

公开(公告)日：2007-05-17

申请号：US11619921

申请日：2007-01-04

申请人： Masayuki SHINOHARA

发明人： Masayuki SHINOHARA

IPC分类号： H04L12/50

CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L49/1561 ,  H04L49/256 ,  H04L49/455

摘要： A packet switching equipment and a switch control system employing the same performs operation of the switch core portion independent of content of decision of an arbiter portion and overall equipment can be constructed with simple control structure. The packet switching equipment includes input buffer portions temporarily storing packets arriving to the input ports and outputting packets with adding labels indicative of destination port numbers, a switch core portion for switching the packets on the basis of labels added to the input buffer portions, and an arbiter portion adjusting input buffer portions to provide output permissions for outputting to the output ports. A sorting network autonomously sorting and concentrating the packets on the basis of the labels added to the packets is employed in the switch core portion.

摘要翻译： 分组交换设备和采用该分组交换设备的交换机控制系统可以独立于仲裁器部分的决策内容和总体设备来执行交换机核心部分的操作，可以用简单的控制结构来构造。 分组交换设备包括临时存储到达输入端口的分组的输入缓冲器部分，并且输出具有指示目的地端口号的添加标签的分组，用于基于添加到输入缓冲器部分的标签来切换分组的交换机核心部分，以及 仲裁器部分调节输入缓冲器部分以提供输出到输出端口的输出许可。 在交换机核心部分中采用基于添加到分组的标签来自动排序和集中分组的分类网络。

公开(公告)号：US20040202178A1

公开(公告)日：2004-10-14

申请号：US09897951

申请日：2001-07-05

申请人： Mitsubishi Denki Kabushiki Kaisha

发明人： Keiji Okubo

IPC分类号： H04L012/28 ,  H04L012/56

CPC分类号： H04L49/1561 ,  H04L12/5601 ,  H04L47/50 ,  H04L49/106 ,  H04L49/20 ,  H04L49/252 ,  H04L49/258 ,  H04L49/30 ,  H04L49/50 ,  H04L2012/5648 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5682

摘要： A packet switching apparatus with a number of lines for simplifying the configuration of the packet switching apparatus by reducing the size of the circuit which is to perform at high speed. The packet switching apparatus is suitable for an ATM switching device, for example. The packet switching apparatus is provided with a first packet switching unit 9 for sorting data packets received through a plurality of input lines 1-1 to 1-n into their corresponding output line groups 7-1 to 7-m, 7-(mnull1) to 7-(2m), and so on, and outputting the sorted data packets to transfer lines 2-1 to 2-i, and the second packet switching unit 10-1 for sorting the data packets received from the transfer line 2-1 into their corresponding output lines 7-1 to 7-m and outputting the sorted data packets. Specifically, the transfer line 2-1 transfers a data packet at a line speed faster than a totaled line speed of the output lines 7-1 to 7-m.

摘要翻译： 一种分组交换装置，具有多条线路，用于通过减小要以高速执行的电路的尺寸来简化分组交换装置的配置。 分组交换装置例如适用于ATM交换装置。 分组交换装置设置有第一分组交换单元9，用于将通过多个输入线1-1至1-n接收的数据分组分类到其对应的输出线组7-1至7-m，7-（m + 1）至7-（2m）等，并将排序的数据分组输出到传送线路2-1至2-i，以及第二分组交换单元10-1，用于对从传输线路2接收的数据分组进行分类 -1到其对应的输出线7-1至7-m，并输出排序的数据分组。 具体地，传输线2-1以比输出线7-1至7-m的总线速度更快的线速度传送数据分组。

公开(公告)号：US06580714B1

公开(公告)日：2003-06-17

申请号：US09184513

申请日：1998-11-02

申请人： Hideki Nishizaki ,  Motoo Nishihara

发明人： Hideki Nishizaki ,  Motoo Nishihara

IPC分类号： H04L1228

CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L49/1561 ,  H04L2012/5679 ,  H04L2012/5681

摘要： An ATM switching system includes a plurality of (m) small-scale n×n ATM switch modules, and a coupling module for coupling the ATM switch modules to one another to implement a large-scale ATM switching system. The coupling module includes m concentrators corresponding to the m ATM switch modules. Each concentrator has a multiplexing block for multiplexing m×n signal sequences into n signal sequences, concentration buffer block including a n×n banyan network for specifying one of ATM switch modules for each effective cell based on a destination signal and a plurality of buffers. The concentrator operates at slow transfer rate in a large-scale ATM system so that the performance of the concentrator does not restrict the scale of the ATM system.

摘要翻译： ATM交换系统包括多个（m）小规模nxn ATM交换机模块，以及用于将ATM交换机模块彼此耦合以实现大规模ATM交换系统的耦合模块。 耦合模块包括对应于m个ATM交换机模块的m个集线器。 每个集中器具有用于将mxn个信号序列复用为n个信号序列的多路复用块，包括nxn榕树网络的浓度缓冲块，用于基于目的地信号和多个缓冲器为每个有效小区指定一个ATM交换模块。 集中器在大规模ATM系统中以低速传输速率运行，从而集中器的性能不会限制ATM系统的规模。

公开(公告)号：US06560232B1

公开(公告)日：2003-05-06

申请号：US09437299

申请日：1999-11-09

申请人： Tsugio Sugawara

发明人： Tsugio Sugawara

IPC分类号： H04L1228

CPC分类号： H04L49/1592 ,  H04L12/5601 ,  H04L47/50 ,  H04L47/6205 ,  H04L49/104 ,  H04L49/1561 ,  H04L49/254 ,  H04L49/508 ,  H04L2012/5679 ,  H04L2012/5683

摘要： First to fourth input buffers stores cells inputted from first to fourth input ports, respectively. Each input buffer is equipped with a main buffer section, a plurality of sub-buffer sections connected to the main buffer section in series and a buffer controller for controlling them. A collision judging section judges whether or not a collision occurs between the cells outputted from each sub-buffer section, and the judged result is sent to a cell converter. The cell converter returns a collision information to the buffer controller in accordance with the judged result, and further sends a cell, which has a victory information since it is judged as a victory over the collision, through a sorter to a self-routing section. The self-routing section outputs the received cell to an output port. This configuration enables a shuffle operation to be carried out in the sub-buffer section and the cell converter to thereby avoid the drop of the throughput.

摘要翻译： 第一至第四输入缓冲器分别存储从第一至第四输入端口输入的单元。 每个输入缓冲器配备有主缓冲器部分，串联连接到主缓冲器部分的多个子缓冲器部分和用于控制它们的缓冲器控制器。 碰撞判断部判定从各个子缓冲部输出的小区之间是否发生冲突，将判定结果发送给小区转换器。 小区转换器根据判断结果向缓冲器控制器返回冲突信息，并且通过分拣机向自路由部分发送具有胜利信息的小区，因为它被认为是碰撞的胜利。 自路由部分将接收到的信元输出到输出端口。 该配置使得能够在子缓冲器部分和小区转换器中执行混洗操作，从而避免吞吐量的下降。