公开(公告)号：US11599099B2

公开(公告)日：2023-03-07

申请号：US16903073

申请日：2020-06-16

Applicant: Palo Alto Research Center Incorporated

Inventor： Morad Behandish ,  Saigopal Nelaturi ,  Johan Dekleer

IPC: G05B19/418 ,  B33Y50/02 ,  B33Y50/00 ,  G06F30/17 ,  G05B19/4093 ,  B29C64/386 ,  G06F111/06 ,  G06F119/18

Abstract: A systematic approach to constructing process plans for hybrid manufacturing is provided. The process plans include arbitrary combinations of AM and SM processes. Unlike the suboptimal conventional practice, the sequence of AM and SM modalities is not fixed beforehand. Rather, all potentially viable process plans to fabricate a desired target part from arbitrary alternating sequences of pre-defined AM and SM modalities are explored in a systematic fashion. Once the state space of all process plans has been enumerated in terms of a partially ordered set of states, advanced artificial intelligence (AI) planning techniques are utilized to rapidly explore the state space, eliminate invalid process plans, for instance, process plans that make no physical sense, and optimize among the valid process plans using a cost function, for instance, manufacturing time and material or process costs.

公开(公告)号：US11537770B2

公开(公告)日：2022-12-27

申请号：US17179975

申请日：2021-02-19

Applicant: President and Fellows of Harvard College

Inventor： Yudong Cao

IPC: G06N10/00 ,  G06F30/327 ,  G06F111/06

Abstract: Mapping of logical qubits to physical qubits is provided. In various embodiments, a first candidate subgraph is selected from a hardware graph. The hardware graph represents a physical quantum circuit. The hardware graph comprises a plurality of nodes corresponding to physical qubits and a plurality of edges corresponding to coupling among the plurality of qubits. An accepted subgraph is determined by: setting the accepted subgraph to be the first candidate subgraph; mapping a quantum circuit comprising a plurality of logical qubits to the accepted subgraph; generating a second candidate subgraph of the hardware graph based on the accepted subgraph; mapping the quantum circuit to the second candidate subgraph; comparing fidelities of the accepted subgraph and the second candidate subgraph for the quantum circuit; if the fidelity of the second candidate subgraph is greater than the fidelity of the accepted subgraph, setting the accepted subgraph to be the second candidate subgraph; if the fidelity of the second candidate subgraph is less than or equal to the fidelity of the accepted subgraph, setting the accepted subgraph to be the second candidate subgraph with a time-dependent probability.

公开(公告)号：US11494534B2

公开(公告)日：2022-11-08

申请号：US16753562

申请日：2018-07-30

Applicant: JFE Steel Corporation

Inventor： Takanobu Saito

IPC: G06F30/20 ,  G06F30/15 ,  G06F30/17 ,  G06F111/06

Abstract: A layered-composite-member shape optimization analysis method includes: setting, as a design space, an optimization target part of a structural body model of an automotive body; generating a layered block model in the set design space, the layered block model including layers, each layer being a three-dimensional element and having material properties different from each other; connecting the generated layered block model to the part of the structural body model of the automotive body; and inputting an analysis condition, performing optimization analysis on the layered block model as an optimization analysis target, and determining an optimum shape of the layered block model.

公开(公告)号：US11387776B2

公开(公告)日：2022-07-12

申请号：US14275689

申请日：2014-05-12

Applicant: SUNRUN, INC.

Inventor： Gary Wayne ,  Billy Hinners

IPC: H02S50/00 ,  H02S50/10 ,  G06F30/13 ,  G06F30/20 ,  G06F111/06 ,  G06F111/20

Abstract: An optimization engine determines an optimal configuration for a solar power system projected onto a target surface. The optimization engine identifies an alignment axis that passes through a vertex of a boundary associated with the target surface and then constructs horizontal or vertical spans that represent contiguous areas where solar modules may be placed. The optimization engine populates each span with solar modules and aligns the solar modules within adjacent spans to one another. The optimization engine then generates a performance estimate for a collection of populated spans. By generating different spans with different solar module types and orientations, the optimization engine is configured to identify an optimal solar power system configuration.

公开(公告)号：US11263375B2

公开(公告)日：2022-03-01

申请号：US16917600

申请日：2020-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED

Inventor： Yi-Lin Chuang ,  Shi-Wen Tan ,  Szu-Ju Huang ,  Shih-Feng Hong

IPC: G06F30/31 ,  G06F111/04 ,  G06F111/06

Abstract: A method, for determining constraints related to a target circuit, includes following operations. First circuit speed results of the target circuit under different candidate constraint configurations are accumulated. Breakthrough probability distributions relative to each of the candidate constraint configurations are determined according to the first circuit speed results. First selected constraint configurations are determined from the candidate constraint configurations by sampling the breakthrough probability distributions. A first budget distribution is determined among the first selected constraint configurations. In response to that the first budget distribution is converged, the first selected constraint configurations in the first budget distribution is utilized for implementing the target circuit and generating an updated circuit speed result of the target circuit.

公开(公告)号：US11259450B2

公开(公告)日：2022-02-22

申请号：US16357494

申请日：2019-03-19

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ryouji Eguchi ,  Hiroki Kobayashi ,  Daisuke Mizokami ,  Takaaki Yokoi

IPC: H05K13/02 ,  H05K13/08 ,  H05K13/04 ,  G06F111/06

Abstract: A method of determining disposition of a component supply unit including a component reel obtained by winding a component accommodating tape accommodating a component and a tape feeder that supplies the component accommodating tape drawn out from the component reel, for determining component supply unit disposition in which the component supply unit is disposed in a holding unit that holds the component supply unit, includes acquiring component supply unit information including information on the number of the component reel and constraint condition information including information related to a layout that is capable of being selected when the component supply unit is disposed in the holding unit, and determining the component supply unit disposition, based on the constraint condition information and the information on the number of the component reel.

公开(公告)号：US11256834B2

公开(公告)日：2022-02-22

申请号：US15979432

申请日：2018-05-14

Applicant: AUTODESK, INC.

Inventor： David Benjamin ,  Danil Nagy ,  Lorenzo Villaggi

IPC: G06F30/17 ,  G06F30/13 ,  G06F111/06

Abstract: A design space analyzer generates a parametric model associated with a design problem. The design space analyzer then discretizes various parameters associated with the model and generates a plurality of sample designs using different combinations of discretized parameters. The design space analyzer also computes one or more metrics for each sample design. In this fashion, the design space analyzer generates a coarse approximation of the design space associated with the design problem. The design space analyzer then evaluates portions of that approximation, at both global and local scales, to identify portions of the design space that meet certain feasibility criteria. Finally, the design space analyzer modifies the design space to facilitate more efficient exploration during optimization.

公开(公告)号：US11030360B2

公开(公告)日：2021-06-08

申请号：US14864478

申请日：2015-09-24

Applicant: SUBARU CORPORATION

Inventor： Kazushige Sato ,  Chikage Murakami ,  Hideo Iso

IPC: G06F30/15 ,  G06F111/04 ,  G06F111/06 ,  G06F111/10

Abstract: An aircraft designing apparatus receives set values of design parameters related to the shape of an intake duct, creates analysis models for an aerodynamic characteristic analysis and a radar-cross-section analysis by using the values of the design parameters, calculates aerodynamic characteristics and radar-cross-section characteristics of the intake duct, and determines whether or not this analytical result satisfies a preset design condition. If it is determined that the analytical result does not satisfy the design condition, the values of the design parameters are updated. The updating of the design parameters, the analyses of the aerodynamic characteristics and the radar-cross-section characteristics, and the determining process are repeated until it is determined that the analytical result satisfies the design condition.

公开(公告)号：US11017149B2

公开(公告)日：2021-05-25

申请号：US16871841

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Ching-Fang Chen ,  Wei-Li Chen ,  Wei-Pin Changchien ,  Yung-Chin Hou ,  Yun-Han Lee

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/30 ,  G06F30/27 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/373 ,  H01L27/02 ,  H05K3/00 ,  G06F30/392 ,  G06F30/394 ,  H01L27/118 ,  G06F30/367 ,  G06F111/06 ,  G06F111/02 ,  G06F119/22

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

公开(公告)号：US11017132B2

公开(公告)日：2021-05-25

申请号：US15568231

申请日：2016-04-21

Applicant: AVL LIST GMBH

Inventor： Michael Kordon ,  Christian Kozlik ,  Kurt Klumaier ,  Ingo Allmer

IPC: G06G7/48 ,  G06F30/20 ,  F02D41/26 ,  G06F11/00 ,  G06F30/17 ,  G05B17/02 ,  G06F30/00 ,  G06F30/15 ,  G06F111/06 ,  F02D41/14

Abstract: The disclosure concerns a method for model-based optimization, especially calibration, of a technical device, especially an internal combustion engine. The method may involve the following steps: detection of at least a first parameter in relation to the technical device being optimized which characterizes a physical quantity; first determination of at least one second parameter in relation to the technical device being optimized by at least a first physical model which characterizes at least one known physical relationship and for which the at least one first parameter is an input parameter; second determination of at least one third parameter by at least one first empirical model based on measurements on a plurality of already-known technical devices of the same kind, especially internal combustion engines, and for which at least the at least one second parameter is an input parameter, wherein the at least one third parameter is suited to characterizing the technical device being optimized and/or to providing a basis for making a change in the technical device being optimized, especially to adjusting a control unit of the technical device being optimized; and outputting the at least one third parameter.