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公开(公告)号：US11070224B1
公开(公告)日：2021-07-20
申请号：US16868894
申请日：2020-05-07
发明人： Hananel Faig , Adam Kaminer , David (Dima) Rochlin , Raanan Ivry
摘要： A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.
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公开(公告)号：US11050430B1
公开(公告)日：2021-06-29
申请号：US16778646
申请日：2020-01-31
发明人： Gregor Feldhaus , Alexander Roth
摘要： A sampling device comprises a clock source that provides a clock frequency, a converter with a receiving port for receiving the clock frequency, and a re-sampler located in a digital domain of the sampling device. The clock source is configured to vary the clock frequency over time. The clock source is configured to forward the clock frequency to the converter in order to change a sampling rate of the converter in dependency of the clock frequency. An output sample rate of the sampling device is fixed.
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公开(公告)号：US10998895B2
公开(公告)日：2021-05-04
申请号：US16814698
申请日：2020-03-10
发明人： Shusuke Kawai
摘要： According to one embodiment, an electronic circuit includes a first delay element, a second delay element, a first hold circuit and a quantization circuit. The first delay element obtains a first signal by delaying a first pulse signal. The second delay element obtains a second signal by delaying the first signal. The first hold circuit holds a first voltage of an input signal corresponding to the first signal. The second hold circuit holds a second voltage of the input signal corresponding to the second signal. The quantization circuit obtains a third signal and a fourth signal each with different rising times based on a second pulse signal, to quantize the first voltage based on the third signal, and to quantize the second voltage based on the fourth signal.
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公开(公告)号：US10979064B2
公开(公告)日：2021-04-13
申请号：US16523575
申请日：2019-07-26
发明人： Martin Kinyua
摘要： An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.
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65.发明申请公开(公告)号：US20210091766A1
公开(公告)日：2021-03-25
申请号：US17006910
申请日：2020-08-31
IPC分类号： H03K17/22 , H03K17/0814 , H03K3/356 , H03M1/00
摘要： The present invention provides a voltage difference measurement circuit comprising a level shifting circuit, an ADC and a calculation circuit. In the operations of the voltage difference measurement circuit, the level shifting circuit adjusts levels of a supply voltage and a ground voltage to generate an adjusted supply voltage and an adjusted ground voltage, respectively. The ADC performs an analog-to-digital converting operation upon the adjusted supply voltage and the adjusted ground voltage to generate a first digital value and a second digital value, respectively. The calculation circuit calculates a voltage difference between the supply voltage and the ground voltage according to the first digital value and the second digital value.
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公开(公告)号：US20210075536A1
公开(公告)日：2021-03-11
申请号：US16732108
申请日：2019-12-31
申请人： Infinera Corporation
发明人： Steven J. Hand
摘要： An example node includes a receiver, a switch circuit, and a transmitter. The receiver is configured to receive a first modulated optical signal including a first plurality of optical subcarriers, and supply a plurality of data streams based on the first plurality of optical subcarriers. Each of the data streams is associated with a corresponding one of the plurality of optical subcarriers. The switch circuit is configured to receive the data streams, and supply the data streams to a plurality of switch outputs. The transmitter is configured to receive the data streams, and supply a second modulated optical signal based on the data streams. The second modulated optical signal carries a second plurality of optical subcarriers. Each of the second plurality of optical subcarriers is associated with a corresponding one of the data streams.
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67.发明授权公开(公告)号：US10944418B2
公开(公告)日：2021-03-09
申请号：US16188217
申请日：2018-11-12
申请人： MEDIATEK INC.
发明人： Ting-Yang Wang , Hung-Yi Hsieh , Tzu-An Wei , Tien-Yu Lo
摘要： The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.
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公开(公告)号：US10931292B1
公开(公告)日：2021-02-23
申请号：US15930598
申请日：2020-05-13
申请人： Ciena Corporation
发明人： Soheyl Ziabakhsh Shalmani , Hazem Beshara , Mohammad Honarparvar , Sadok Aouini , Christopher Kurowski , Naim Ben-Hamida
摘要： Described are apparatus and methods for successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with factoring and background clock calibration. An apparatus includes a SAR ADC configured to, in response to receiving an enable flag based on detection of an acquisition clock with a first logic state sent by a controller, sample and convert a pair of differential input signals using a sampling clock to obtain a defined number of samples in an acquisition clock cycle and a factoring circuit configured to obtain the defined number of samples from the SAR ADC using a capturing clock based on the sampling clock, factor the defined number of samples, and send a factored samples ready flag to the controller.
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公开(公告)号：US20210028625A1
公开(公告)日：2021-01-28
申请号：US17040055
申请日：2019-02-27
发明人： Sadayuki INOUE , Tomihiro TAKANO
摘要： A solar cell power conversion device is disposed between a solar cell and a consumer premises distribution system. A storage battery power conversion device is disposed between a storage battery and the consumer premises distribution system. When an AC effective voltage in the consumer premises distribution system deviates from a voltage range defined in accordance with dead zone information transmitted from HEMS, system voltage stabilization control for returning the AC effective voltage to fall within the voltage range is performed by control of active power and reactive power that are output from a first DC/AC conversion circuit and a second DC/AC conversion circuit.
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公开(公告)号：US10833790B2
公开(公告)日：2020-11-10
申请号：US16750787
申请日：2020-01-23
发明人： Nicholas Nicas , Todd Andrew Fryer , David Irvin
IPC分类号： H04N13/25 , H04J14/02 , H03M1/12 , H04B10/516 , H04N13/239 , H03M1/00
摘要： Aspects of the subject disclosure may include, for example, a process that encodes a number of digital signals representing image data captured by a video camera, the image data being provided by the video camera in accordance with a 4K ultra-high definition (4K-UHD) standard. The number of digital signals are provided to a multiplexing unit that outputs a multiplexed signal including a number of optical wavelengths, the multiplexed signal being transmitted on a single fiber-optic cable unidirectionally from the multiplexing unit to a presentation device. The multiplexed signal is transmitted on the single cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed.
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