公开(公告)号：US5654712A

公开(公告)日：1997-08-05

申请号：US510388

申请日：1995-08-02

申请人： Andrew Cheng

发明人： Andrew Cheng

IPC分类号： G06F1/22 ,  H03K19/173 ,  H03M5/20 ,  H03M1/10

CPC分类号： H03K19/1732 ,  G06F1/22 ,  H03M5/20

摘要： An encoding control device includes a voltage provider providing different voltage levels at different instances, a data control device electrically connected to the voltage provider and outputting data respectively corresponding to the voltage levels, and an encoding device electrically connected to the data control device for encoding according to the data. The present encoding control device effectively reduces the pin number of an IC package.

摘要翻译： 编码控制装置包括在不同情况下提供不同电压电平的电压提供器，电连接到电压提供器并输出分别对应于电压电平的数据的数据控制装置，以及电连接到数据控制装置进行编码的编码装置， 数据。 本编码控制装置有效地减少了IC封装的引脚数。

公开(公告)号：US5258999A

公开(公告)日：1993-11-02

申请号：US770507

申请日：1991-10-03

申请人： Thomas L. Wernimont ,  Kevin L. Kloker ,  Clif Liu

发明人： Thomas L. Wernimont ,  Kevin L. Kloker ,  Clif Liu

IPC分类号： G06F11/10 ,  G06F1/22 ,  H04B1/20 ,  H04L1/00 ,  H04L29/08 ,  H04B1/38 ,  H04L5/16

CPC分类号： H04L1/0061 ,  G06F1/22 ,  H04B1/207

摘要： An interface transceiver (16) circuit and method for communicating transceiver control and status information between a signal processor (20) and either an audio source (12) or an audio sink (24). During transmission of digital audio data from audio source (12) and signal processor (20), a comparator (49) compares a cyclic redundancy check (CRCC) byte of a block of channel status information to a theoretical CRCC byte generated by a CRC generator (48). By comparing actual and theoretical CRCC bytes, comparator (49) indicates in a single bit whether audio data was transmitted correctly. Remaining bits of the CRCC byte are then used to transfer status information corresponding to transceiver (16). Similarly, during transmission of digital data from signal processor (20) to audio sink (24), a parity bit of a subframe of the digital data is used to transfer programming information from signal processor (20) to audio sink (24).

摘要翻译： 一种用于在信号处理器（20）和音频源（12）或音频接收器（24）之间传送收发器控制和状态信息的接口收发器（16）电路和方法。 在从音频源（12）和信号处理器（20）传输数字音频数据期间，比较器（49）将信道状态信息块的循环冗余校验（CRCC）字节与CRC发生器产生的理论CRCC字节进行比较 （48）。 通过比较实际和理论CRCC字节，比较器（49）在单个位中指示音频数据是否被正确传输。 然后使用CRCC字节的剩余比特来传送对应于收发信机（16）的状态信息。 类似地，在将数字数据从信号处理器（20）传输到音频宿（24）期间，数字数据的子帧的奇偶校验位用于将编程信息从信号处理器（20）传送到音频宿（24）。

公开(公告)号：US4897651A

公开(公告)日：1990-01-30

申请号：US919137

申请日：1986-10-15

申请人： Filippo DeMonte

发明人： Filippo DeMonte

IPC分类号： H03M11/14 ,  G06F1/22 ,  G06F3/023 ,  H01H13/705

CPC分类号： H01H13/705 ,  G06F1/22 ,  G06F3/0238 ,  H01H2219/012 ,  H01H2239/02

摘要： The key comprises a movable part guided in a fixed support on a base plate and contacts which are closed when the key is depressed against the action of a return spring. The symbol associated with the key is displayed through a window in the key top by an LCD device with a matrix of display areas controlled by an integrated circuit bonded to the underside of the LCD device and fed with signals from the CPU via conductors which enable the integrated circuit to be programmed to define the symbol to be displayed, whereby the keys of a keyboard can be set to match the language currently being used. In an alternative embodiment the key is supported by a flat cable connected with an input circuit of the keyboard and the terminals of the LCD device.

摘要翻译： 钥匙包括在基板上的固定支撑件中被引导的可动部分，以及抵抗复位弹簧的作用而使键被按下的触点。 与钥匙相关联的符号通过液晶显示装置通过键顶部的窗口显示，其具有由集成电路控制的显示区域矩阵，该集成电路被连接到LCD装置的下侧，并通过导体馈送来自CPU的信号， 集成电路被编程以定义要显示的符号，由此可以将键盘的键设置为与当前使用的语言相匹配。 在替代实施例中，键由与键盘的输入电路和LCD装置的端子连接的扁平电缆支撑。

公开(公告)号：US4677548A

公开(公告)日：1987-06-30

申请号：US655111

申请日：1984-09-26

申请人： John J. Bradley

发明人： John J. Bradley

IPC分类号： G06F1/22 ,  G06F12/06 ,  G06F15/78 ,  G06F1/00 ,  G06F13/00

CPC分类号： G06F15/7842 ,  G06F1/22 ,  G06F12/0623

摘要： A chip implemented in new technology is designed to include expandable levels of new functionality. The chip includes compatibility circuits which connect to a number of pins which are unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered levels of functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at high speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with a selectable level of new functionality at the same higher speed and improved performance.

摘要翻译： 以新技术实现的芯片旨在包括可扩展级别的新功能。 该芯片包括连接到在现有计算机系统中替代的芯片中未使用的多个引脚的兼容性电路。 兼容性电路连接到包含新添加或改变的功能级别的新芯片的内部部分。 新芯片就像以前的芯片一样安装在现有的计算机系统中。 当这样安装时，兼容性电路使得新芯片能够以与替换的芯片相同的方式工作，但是以高速度并且具有改进的性能。 当新芯片安装在其设计的系统中时，兼容性电路使芯片能够以相同的更高速度和更高性能的可选级别的新功能运行。

公开(公告)号：US4654789A

公开(公告)日：1987-03-31

申请号：US596756

申请日：1984-04-04

申请人： Eugene Nusinov ,  John J. Bradley

发明人： Eugene Nusinov ,  John J. Bradley

IPC分类号： G06F1/22 ,  G06F12/06 ,  G06F1/00 ,  G06F13/00

CPC分类号： G06F12/0623 ,  G06F1/22 ,  H01L2924/0002

摘要： A chip implemented in newer technology is designed to include new functionality. The chip includes compatibility circuits which connect to a pin which is unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at higher speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with the new functionality at the same higher speed and improved performance as compared to the replaced chip.

摘要翻译： 以较新技术实现的芯片旨在包括新功能。 该芯片包括连接到在现有计算机系统中替代的芯片中未使用的引脚的兼容性电路。 兼容性电路连接到包含新添加或改变的功能的新芯片的内部部分。 新芯片就像以前的芯片一样安装在现有的计算机系统中。 当这样安装时，兼容性电路使新芯片能够以与更换的芯片相同的方式工作，但是以更高的速度和更好的性能。 当新芯片安装在其设计的系统中时，兼容性电路使得芯片能够以与更换的芯片相同的更高速度和更高的性能与新的功能一起运行。

公开(公告)号：US4628480A

公开(公告)日：1986-12-09

申请号：US540573

申请日：1983-10-07

申请人： William M. Floyd

发明人： William M. Floyd

IPC分类号： G06F13/14 ,  G06F1/22 ,  G06F1/24 ,  G06F9/445 ,  G06F13/00 ,  G06F1/00

CPC分类号： G06F9/4403 ,  G06F1/22 ,  G06F1/24

摘要： Arrangement for the input of address data to an integrated circuit (IC) via the same input/output (I/O) terminal pins utilized for the transfer of data is disclosed. The I/O data pins each have an output data latch and an address latch connected to the respective pin and positioned internally of the circuit's interface. A logic level is applied to each of those I/O data pins via a respective external resistor for normally biasing the pin to that logic level. A further I/O pin at the circuit's interface is connected to a common conductor positioned externally of the interface. Diodes are connected between selected ones of the I/O data pins and the common conductor in accordance with a desired address. A level controller responds to a power-on-reset (POR) gating signal to switch the common conductor between a high impedance state and a logic level which effects conduction by the diodes, to enter address data bits. Address latches in the IC store the entered address data bits. The end of the gating signal enters the address bits into their respective latches. Output of data to the I/O data pins is via respective tri-stated transmit devices having their inputs connected to the outputs of respective data latches, and serves to extend that data value or its inverse to a respective I/O pin when enabled upon cessation of the POR signal.

摘要翻译： 公开了通过用于传输数据的相同输入/输出（I / O）端子引脚将输入地址数据输入到集成电路（IC）的布置。 I / O数据引脚各自具有输出数据锁存器和连接到相应引脚并位于电路接口内部的地址锁存器。 逻辑电平通过相应的外部电阻器施加到每个I / O数据引脚，用于将引脚正常地偏置到该逻辑电平。 电路接口上的另一个I / O引脚连接到位于接口外部的公共导体。 根据期望的地址，二极管连接在I / O数据引脚和公共导体的选定引脚之间。 电平控制器响应上电复位（POR）门控信号，以在高阻抗状态和导致二极管导通的逻辑电平之间切换公共导体，以输入地址数据位。 IC中的地址锁存器存储输入的地址数据位。 门控信号的结尾将地址位输入到它们各自的锁存器中。 将数据输出到I / O数据引脚是经由相应的三态发送器件，其输入端连接到相应的数据锁存器的输出，并且用于在使能时将该数据值或其相应的I / O引脚扩展到相应的I / O引脚 停止POR信号。

公开(公告)号：US4610000A

公开(公告)日：1986-09-02

申请号：US663926

申请日：1984-10-23

申请人： Robert D. Lee

发明人： Robert D. Lee

IPC分类号： G06F1/22 ,  G06F12/06 ,  G11C11/00 ,  G11C11/40

CPC分类号： G11C11/005 ,  G06F1/22 ,  G06F12/0638

摘要： An integrated circuit contains ROM, ROM patch and RAM memories on a common substrate with a standard pinout. The ROM and RAM fill the address space allowed by the address pins. Control of the patch memory without the use of special control pins is accomplished by writing to a ROM address with the standard control pins set for a RAM write. Various control functions are made of a series of standard-cycle read and write operations.

摘要翻译： 集成电路在标准引脚排列的公共基板上包含ROM，ROM补片和RAM存储器。 ROM和RAM填充地址引脚允许的地址空间。 通过使用为RAM写入设置的标准控制引脚写入ROM地址来实现对不使用特殊控制引脚的补丁存储器的控制。 各种控制功能由一系列标准循环读写操作组成。

公开(公告)号：US4306163A

公开(公告)日：1981-12-15

申请号：US9116

申请日：1979-02-05

申请人： Henry M. Blume, Jr. ,  David A. Stamm ,  David L. Budde

发明人： Henry M. Blume, Jr. ,  David A. Stamm ,  David L. Budde

IPC分类号： G06F1/22 ,  G06F15/78 ,  H03K19/0185 ,  H03K19/0944 ,  H03K17/26 ,  H03K19/00

CPC分类号： G06F1/22 ,  G06F15/7814 ,  H03K19/01855 ,  H03K19/09443

摘要： A buffer utilizing MOS devices for coupling a computer input data line and a computer output data line to a single input/output port is disclosed. The buffer receives a control signal generated by computer port control means at the beginning of any buffer cycle when data is to be accepted by the buffer.

摘要翻译： 公开了一种使用MOS器件的缓冲器，用于将计算机输入数据线和计算机输出数据线耦合到单个输入/输出端口。 当数据被缓冲器接受时，缓冲器在任何缓冲器周期开始时接收由计算机端口控制装置产生的控制信号。

公开(公告)号：US4064399A

公开(公告)日：1977-12-20

申请号：US672277

申请日：1976-03-31

申请人： Susumu Muranaka

发明人： Susumu Muranaka

IPC分类号： G06F15/02 ,  G06F1/22 ,  G06F3/023 ,  H03M11/20

CPC分类号： G06F1/22 ,  G06F3/023

摘要： An electronic calculator comprises a semiconductor integrated circuit and an input keyboard which includes the series connection of a condition switch and an operation key, thereby minimizing the number of interconnections between the semiconductor integrated circuit and the keyboard.

摘要翻译： 电子计算器包括半导体集成电路和输入键盘，其包括状态开关和操作键的串联连接，从而最小化半导体集成电路和键盘之间的互连的数量。

公开(公告)号：US2065694A

公开(公告)日：1936-12-29

申请号：US74676434

申请日：1934-10-04

申请人： COLLIS COMPANY

发明人： GLENN HATCHER

IPC分类号： G01N33/08 ,  G06F1/22

CPC分类号： G01N33/085