公开(公告)号：US20210167729A1

公开(公告)日：2021-06-03

申请号：US17171490

申请日：2021-02-09

Applicant: STMicroelectronics SA

Inventor： Lionel VOGT

IPC: H03D1/18 ,  H03D1/06 ,  H03D1/22 ,  H04L27/06 ,  G01R19/04 ,  H03D3/00 ,  H04L27/233

Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

公开(公告)号：US10971489B2

公开(公告)日：2021-04-06

申请号：US16406534

申请日：2019-05-08

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/06 ,  H01L49/02

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

公开(公告)号：US20210096183A1

公开(公告)日：2021-04-01

申请号：US17031716

申请日：2020-09-24

Applicant: STMICROELECTRONICS SA

Inventor： Ricardo GOMEZ GOMEZ ,  Sylvain CLERC

IPC: G01R31/319 ,  G01R31/3185 ,  G01R31/3193 ,  G01R31/317

Abstract: A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The comparing and the shifting and storing are repeated until all the stored test data has been compared. The at least three devices may have a same functionality and a same structure.

公开(公告)号：US10951168B2

公开(公告)日：2021-03-16

申请号：US16739287

申请日：2020-01-10

Applicant: STMicroelectronics SA

Inventor： Lionel Vogt

IPC: H03D1/18 ,  H03D1/06 ,  H03D1/22 ,  H04L27/06 ,  G01R19/04 ,  H03D3/00 ,  H04L27/233 ,  H03F3/20

Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

公开(公告)号：US20200381833A1

公开(公告)日：2020-12-03

申请号：US16889240

申请日：2020-06-01

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Frederic GIANESELLO ,  Didier CAMPOS

IPC: H01Q9/04 ,  H01Q5/357 ,  H01Q1/22 ,  H01Q21/28

Abstract: A first independent unit includes a support substrate with an integrated network of electrical connections. An electronic integrated circuit chip is mounted above a front face of the support substrate. A second independent unit includes a dielectric support. The second independent unit is stacked above the first independent unit on a side of the front face of the first independent unit. An electromagnetic antenna includes an exciter element and a resonator element. The exciter element provided at the support substrate. The resonator element is provided at the dielectric support.

公开(公告)号：US10804275B2

公开(公告)日：2020-10-13

申请号：US16199810

申请日：2018-11-26

Applicant: STMicroelectronics SA

Inventor： Hassan El Dirani ,  Thomas Bedecarrats ,  Philippe Galy

IPC: H01L27/108 ,  G11C11/39 ,  H01L27/102 ,  H01L29/74 ,  G11C11/402 ,  G11C11/409

Abstract: A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.

公开(公告)号：US10658197B2

公开(公告)日：2020-05-19

申请号：US15390077

申请日：2016-12-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Nicolas Posseme ,  Maxime Garcia-Barros ,  Yves Morand

IPC: H01L21/324 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/223 ,  H01L21/322 ,  H01L21/447 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.

公开(公告)号：US20200112301A1

公开(公告)日：2020-04-09

申请号：US16654261

申请日：2019-10-16

Applicant: STMicroelectronics SA

Inventor： Sylvain ENGELS ,  Alain AURAND ,  Etienne MAURIN

IPC: H03K3/356 ,  H03K3/3562 ,  H01L23/528 ,  H03K19/0948 ,  H01L27/02

Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).

公开(公告)号：US20200099554A1

公开(公告)日：2020-03-26

申请号：US16569999

申请日：2019-09-13

Applicant: STMicroelectronics SA

Inventor： Marc Houdebine

IPC: H04L27/00

Abstract: A method of contactless communication can be performed between an object and a reader using active load modulation. A synchronization process is performed between a first carrier signal transmitted by the reader and having a reference frequency, and a second carrier signal extracted from an output signal of a controlled oscillator of a digital phase-locked loop of the object. In the synchronization process, as long as a locking of the loop has not been detected, the frequency of the output signal of the oscillator is latched on a frequency that is a multiple of the reference frequency. Once the locking has been detected, the latching continues while controlling the oscillator with a second control signal generated from a second value obtained.

公开(公告)号：US20200057200A1

公开(公告)日：2020-02-20

申请号：US16662810

申请日：2019-10-24

Applicant: STMicroelectronics SA

Inventor： Cédric Durand ,  Frédéric Gianesello ,  Folly Eli Ayi-Yovo

IPC: G02B6/30 ,  B23K26/0622 ,  B23K26/402 ,  B23K26/364 ,  C03C23/00 ,  G02B6/138 ,  G02B6/136 ,  C03C17/09

Abstract: A method of manufacturing an optical device is disclosed. The method includes scanning along a curved path at a first surface of a glass plate with a laser beam directed orthogonally to the first surface to form a trench according to a pattern of a waveguide. The curved path is coincident with a longitudinal axis of the waveguide. The method further includes filling the trench with a material having an index different from that of glass to form the waveguide and, after filling the trench, depositing a cladding layer.