公开(公告)号：US07133817B2

公开(公告)日：2006-11-07

申请号：US10074265

申请日：2002-02-12

Applicant: Nicholas Pavey

Inventor： Nicholas Pavey

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5022

Abstract: A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals within the hardware design are recorded. Each trace includes signal data, time data and at least the internal signals associated with the components. The traces are processed to ascertain whether the plurality of components simultaneously had the signal values associated with the state, thereby to ascertain whether the state was achieved.

公开(公告)号：US20060184775A1

公开(公告)日：2006-08-17

申请号：US11384024

申请日：2006-03-17

Applicant: Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

Inventor： Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

IPC: G06F9/44

CPC classification number: G06F11/3656 ,  G06F9/3842

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract translation: 描述了一种具有增强型集成调试功能的计算机系统。 根据一个方面，执行指令序列的逐步执行，其中每个指令被保护。 如果在保护解决之后，执行指令，则执行转移程序。 如果指令未提交，则执行该顺序中的下一条指令。 根据另一方面，可以通过读取与调试指令相关联的失速属性，或响应来自片上仿真单元的失速命令，在解码单元处设置失速状态。

公开(公告)号：US20060138981A1

公开(公告)日：2006-06-29

申请号：US11298544

申请日：2005-12-09

Applicant: Saul Darzy ,  Jean-Francois Garnier

Inventor： Saul Darzy ,  Jean-Francois Garnier

IPC: H02P7/06

CPC classification number: H02P7/29

Abstract: There is provided a controller for a DC motor drive transistor which controls a parameter of a motor, the transistor being of PNP or NPN type, and the controller comprising a detection circuit, adapted to determine whether the DC motor drive transistor is of the PNP or NPN type and a driver circuit, adapted to sink current from the PNP transistor if it is determined that a PNP transistor is present, or source current into the NPN transistor if it is determined that an NPN transistor is present.

Abstract translation: 提供了一种用于控制电动机参数的直流电动机驱动晶体管的控制器，该晶体管是PNP或NPN型，并且该控制器包括一个检测电路，适用于确定直流电动机驱动晶体管是否为PNP， 如果确定存在PNP晶体管，则NPN型和驱动电路适于从PNP晶体管吸收电流，或者如果确定存在NPN晶体管，则该源极电流流入NPN晶体管。

公开(公告)号：US07039831B2

公开(公告)日：2006-05-02

申请号：US09778466

申请日：2001-02-07

Applicant: Mark Phillips

Inventor： Mark Phillips

IPC: G06F11/00

CPC classification number: G06F11/3656

Abstract: During debugging of target system by a host system, s single stack is used for an exception by a set of applications running on the processor of the target. To achieve this, the stack is dynamically loaded by the host to a reserved memory region, and a vector of the target is set to point to that reserved memory region. The exception handlers of each application then use the vector to access the stack.

Abstract translation: 在主机系统对目标系统的调试期间，单个堆栈用于在目标处理器上运行的一组应用程序的异常。 为了实现这一点，堆栈被主机动态地加载到保留的存储器区域，并且目标的向量被设置为指向该保留的存储器区域。 每个应用程序的异常处理程序然后使用向量访问堆栈。

公开(公告)号：US07031903B2

公开(公告)日：2006-04-18

申请号：US09981664

申请日：2001-10-16

Applicant: Anthony Debling

Inventor： Anthony Debling

IPC: G06F9/455

CPC classification number: G06F11/3636 ,  G06F11/3656

Abstract: A communication device for a target integrated circuit chip having a digital processor, an on-chip emulator for controlling the digital processor and for collecting operation data from the digital processor for communicating to off-chip circuitry, and a target on-chip universal serial bus interface connected to the on-chip emulator, the communication device including an Ethernet port, an universal serial bus port and a further integrated circuit chip having on-chip universal serial bus interface, the on-chip Ethernet interface being connected to the Ethernet port, the interfaces being connected to the processing circuitry for translating between Ethernet protocol data on an Ethernet bus connected to the Ethernet port and universal serial bus data for the target on-chip universal serial bus interface.

Abstract translation: 一种用于具有数字处理器的目标集成电路芯片的通信装置，用于控制数字处理器并用于从数字处理器收集操作数据以用于与芯片外电路进行通信的片上仿真器，以及目标片上通用串行总线 接口连接到片上仿真器，通信设备包括以太网端口，通用串行总线端口和具有片上通用串行总线接口的另外的集成电路芯片，片上以太网接口连接到以太网端口， 该接口连接到处理电路，用于在连接到以太网端口的以太网总线上的以太网协议数据和用于目标片上通用串行总线接口的通用串行总线数据之间进行转换。

公开(公告)号：US07010732B2

公开(公告)日：2006-03-07

申请号：US10068307

申请日：2002-02-06

Applicant: Steven Firth ,  William Bryan Barnes

Inventor： Steven Firth ,  William Bryan Barnes

IPC: G11C29/00 ,  G01R31/28

CPC classification number: G11C29/14 ,  G11C29/48

Abstract: Test circuitry for testing an integrated circuit, the integrated circuit being configurable to accept input data from stimulus scan cells and to provide output data to response scan cells, the test circuitry including stimulus circuitry for providing test data to the integrated circuit; input selection means operable to control which of the test data and the input data are received at the integrated circuit; capture circuitry for capturing output data from the integrated circuit and generating response data; output selection means operable to select which of the output data and the response data are received by the response scan cells.

公开(公告)号：US07007272B2

公开(公告)日：2006-02-28

申请号：US09974175

申请日：2001-10-10

Applicant: Stephen Clarke

Inventor： Stephen Clarke

IPC: G06F9/45

CPC classification number: G06F8/445

Abstract: This patent describes a method of compiling a computer program from a sequence of computer instructions including a plurality of first, set branch, instructions which each identify a target address for a branch and a plurality of associated second, effect branch instructions which each implement a branch to a target address. The method comprising the steps of: reading the computer instructions in blocks; allocating each set branch instruction to an initial node in a dominator tree, the initial node being the node which contains the corresponding effect branch instruction; for the first determining the effect of migrating set branch instructions to each of a set of ancestor nodes in the dominator tree based on a performance cost parameter and selecting an ancestor node with the best performance cost parameter; locating said set branch instruction at the selected ancestor node. Repeating the determining and locating steps for each of the set branch instructions

公开(公告)号：US06990100B2

公开(公告)日：2006-01-24

申请号：US09809726

申请日：2001-03-15

Applicant: Douglas John Turner

Inventor： Douglas John Turner

IPC: H04L12/28

CPC classification number: H04L69/22 ,  H04L69/08

Abstract: A method of converting a packet of data from a source format to a target format, the packet including a type indicator and at least one data field, the method including the steps of storing a table for each packet type, each table including for each data field of that packet type a value representative of a storage requirement in memory and a corresponding field descriptor denoting the nature of the data field; receiving a packet in a source format; identifying the type of packet from the type indicator; accessing the stored table for the type of packet identified and thus obtaining for each data field a value representative of a storage requirement in memory and a field descriptor for that field; and using the value and the field descriptor to load the packet into a target memory according to the target format specified by the field descriptor.

Abstract translation: 一种将来自源格式的数据分组转换为目标格式的方法，所述分组包括类型指示符和至少一个数据字段，所述方法包括以下步骤：为每个分组类型存储表，每个表包括每个数据 该分组的字段表示存储器中的存储需求的值，以及表示数据字段的性质的对应的字段描述符; 以源格式接收数据包; 从类型指示符中识别分组的类型; 访问所存储的表，以识别所识别的分组的类型，从而为每个数据字段获得代表存储器中的存储需求的值和该字段的字段描述符; 并使用该值和字段描述符根据字段描述符指定的目标格式将数据包加载到目标存储器中。

公开(公告)号：US20050285960A1

公开(公告)日：2005-12-29

申请号：US11165314

申请日：2005-06-23

Applicant: Matthew Purcell ,  Robert Henderson ,  J.E.D. Hurwitz

Inventor： Matthew Purcell ,  Robert Henderson ,  J.E.D. Hurwitz

IPC: H04N5/217 ,  H04N5/357 ,  H04N5/378 ,  H04N5/335

CPC classification number: H04N5/3575 ,  H04N5/378

Abstract: The readout circuit, for an image sensing pixel array, is arranged to perform correlated double sampling and includes readout circuitry which is capable of learning its own internal offset and the offset of both its inputs. In the process of correlated double sampling, one of two sampling capacitors can be made smaller, as the thermal noise it creates is learned. The reduction of size of the appropriate sampling capacitor enables the size of a column multiplexer to be reduced without affecting its noise contribution.

Abstract translation: 用于图像感测像素阵列的读出电路被布置成执行相关的双重采样，并且包括能够学习其自身的内部偏移和其两个输入的偏移的读出电路。 在相关双采样过程中，可以使两个采样电容器之一变小，因为它产生的热噪声被学习。 减小适当采样电容器的尺寸使得能够减小列多路复用器的尺寸而不影响其噪声贡献。

公开(公告)号：US20050285946A1

公开(公告)日：2005-12-29

申请号：US11154207

申请日：2005-06-16

Applicant: Jeffrey Raynor

Inventor： Jeffrey Raynor

IPC: G03B17/00 ,  G03B17/18 ,  H04N1/21 ,  H04N5/225 ,  H04N5/232 ,  H04N5/335

CPC classification number: H04N5/232 ,  G03B17/18 ,  H04N5/335 ,  H04N2201/3254

Abstract: An orientation sensor for use with an image sensor is provided, which includes at least two polarizers with different orientations and associated photodetectors and a signal processing unit. The orientation sensor can be incorporated in a digital camera. When the camera is exposed to daylight, which is polarized, the relative outputs from the differently oriented polarizers can be compared to record the orientation of the camera. This orientation can be stored with the image data so that a user does not have to manually change the orientation of an image on an image display device.

Abstract translation: 提供了一种与图像传感器一起使用的方向传感器，其包括具有不同取向的至少两个偏振器和相关联的光电检测器以及信号处理单元。 方向传感器可以结合在数码相机中。 当相机暴露在日光下时，这是极化的，可以比较来自不同方向的偏振器的相对输出以记录相机的方向。 该方向可以与图像数据一起存储，使得用户不必手动地改变图像显示装置上的图像的方向。