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    Hyper page mode control circuit for a semiconductor memory device
    72.
    发明授权
    Hyper page mode control circuit for a semiconductor memory device 失效
    用于半导体存储器件的超页模式控制电路

    公开(公告)号：US5835449A

    公开(公告)日：1998-11-10

    申请号：US756144

    申请日：1996-11-27

    Applicant: Jin-Young Lee

    Inventor： Jin-Young Lee

    IPC: G11C11/417 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409

    CPC classification number: G11C7/1048 ,  G11C7/1024

    Abstract: An output control circuit for a semiconductor memory device allows the output data to be controlled by a write enable line and/or an output enable line in hyper page mode. An output write enable control signal is generated in response to a column address strobe signal, an output enable signal and a write enable signal. A precharge signal is generated in response to the output write enable control signal, thereby allowing a data bus line to be precharged in hyper page mode. The output enable signal and the write enable signal can be selectively coupled to an output write enable control signal generating circuit to allow the output control circuit to operate in different modes. A trigger signal, which controls a data output buffer and driver circuit, is controlled in response to a latch signal. The latch signal is generated by latching the write enable signal in response to the column address strobe signal. The output control circuit allows the data bus line to be precharged between consecutive bits of output data in hyper page mode.

    Abstract translation: 用于半导体存储器件的输出控制电路允许通过写入使能线和/或超级页面模式的输出使能线来控制输出数据。 响应于列地址选通信号，输出使能信号和写使能信号，产生输出写使能控制信号。 响应于输出写使能控制信号产生预充电信号，从而允许数据总线线以超页模式预充电。 输出使能信号和写使能信号可选择性地耦合到输出写入使能控制信号发生电路，以允许输出控制电路以不同的模式工作。 控制数据输出缓冲器和驱动电路的触发信号是根据锁存信号进行控制的。 锁存信号是通过响应于列地址选通信号锁存写使能信号来产生的。 输出控制电路允许数据总线在超级页模式的输出数据的连续位之间进行预充电。

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