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    Transactional memory that supports a put with low priority ring command
    71.
    发明授权
    Transactional memory that supports a put with low priority ring command 有权
    支持低优先级环指令的事务内存

    公开(公告)号：US08972630B1

    公开(公告)日：2015-03-03

    申请号：US14037226

    申请日：2013-09-25

    Applicant: Netronome Systems, Inc.

    Inventor： Gavin J. Stark

    IPC: G06F3/00 ,  G06F5/00 ,  G06F9/46 ,  G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0683 ,  G06F9/467 ,  H04L49/9031

    Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

    Abstract translation: 事务存储器（TM）包括控制电路管线和相关联的存储器单元。 存储单元存储多个环。 对于每个环，流水线保持头指针和尾指针。 管道的环操作阶段将维护指针，因为值被放置在环上并被取消。 如果环未满，则put命令会使TM将值放入环中。 如果环不为空，则get命令使TM取环， 如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。 从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。

    TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND
    72.
    发明申请
    TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND 有权

    公开(公告)号：US20140258644A1

    公开(公告)日：2014-09-11

    申请号：US14287012

    申请日：2014-05-24

    Applicant: Netronome Systems, Inc.

    Inventor： Gavin J. Stark

    IPC: G06F9/46 ,  G06F13/16

    CPC classification number: G06F9/467 ,  G06F12/00 ,  G06F13/1615 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4234 ,  H04L45/745 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.

    High-speed and memory-efficient flow cache for network flow processors
    74.
    发明授权
    High-speed and memory-efficient flow cache for network flow processors 有权

    公开(公告)号：US10671530B1

    公开(公告)日：2020-06-02

    申请号：US16252406

    申请日：2019-01-18

    Applicant: Netronome Systems, Inc.

    Inventor： Edwin S. Peer

    IPC: G06F12/00 ,  G06F12/0802 ,  H04L9/06 ,  G06F12/14

    Abstract: The flow cache of a network flow processor (NFP) stores flow lookup information in cache lines. Some cache lines are stored in external bulk memory and others are cached in cache memory on the NFP. A cache line includes several lock/hash entry slots. Each slot can store a CAM entry hash value, associated exclusive lock status, and associated shared lock status. The head of a linked list of keys associated with the first slot is implicitly pointed to. For the other lock/entry slots, the cache line stores a head pointer that explicitly points to the head. Due to this architecture, multiple threads can simultaneously process packets of the same flow, obtain lookup information, and update statistics in a fast and memory-efficient manner. Flow entries can be added and deleted while the flow cache is handling packets without the recording of erroneous statistics and timestamp information.

    Multiprocessor system having efficient and shared atomic metering resource
    75.
    发明授权
    Multiprocessor system having efficient and shared atomic metering resource 有权

    公开(公告)号：US10366019B1

    公开(公告)日：2019-07-30

    申请号：US15256590

    申请日：2016-09-04

    Applicant: Netronome Systems, Inc.

    Inventor： Gavin J. Stark

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

    Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM) that stores instructions and data, a system interface block, a posted transaction interface block, and an atomics block. Each processor is coupled to the system interface block via its AHB-S bus. The posted transaction interface block and the atomics block are shared resources that a processor can use via the same system interface block. A processor causes the atomics block to perform an atomic metering operation by doing an AHB-S write to a particular address in shared address space. The system interface block translates information from the AHB-S write into an atomics command, which in turn is converted into pipeline opcodes that cause a pipeline within the atomics block to perform the operation. An atomics response communicates result information which is stored into the system interface block. The processor reads the result information by reading from the same address.

    High-speed and memory-efficient flow cache for network flow processors
    76.
    发明授权
    High-speed and memory-efficient flow cache for network flow processors 有权

    公开(公告)号：US10204046B1

    公开(公告)日：2019-02-12

    申请号：US15356562

    申请日：2016-11-19

    Applicant: Netronome Systems, Inc.

    Inventor： Edwin S. Peer

    IPC: G06F12/00 ,  G06F12/0802 ,  G06F12/14 ,  H04L9/06

    Abstract: The flow cache of a network flow processor (NFP) stores flow lookup information in cache lines. Some cache lines are stored in external bulk memory and others are cached in cache memory on the NFP. A cache line includes several lock/hash entry slots. Each slot can store a CAM entry hash value, associated exclusive lock status, and associated shared lock status. The head of a linked list of keys associated with the first slot is implicitly pointed to. For the other lock/entry slots, the cache line stores a head pointer that explicitly points to the head. Due to this architecture, multiple threads can simultaneously process packets of the same flow, obtain lookup information, and update statistics in a fast and memory-efficient manner. Flow entries can be added and deleted while the flow cache is handling packets without the recording of erroneous statistics and timestamp information.

    Addressless merge command with data item identifier
    77.
    发明授权
    Addressless merge command with data item identifier 有权

    公开(公告)号：US10146468B2

    公开(公告)日：2018-12-04

    申请号：US14492013

    申请日：2014-09-20

    Applicant: Netronome Systems, Inc.

    Inventor： Salma Mirza ,  Gavin J. Stark

    IPC: G06F12/00 ,  G06F3/06 ,  G06F13/28 ,  H04L12/00 ,  H04L29/08 ,  H04L12/64 ,  H04L29/06 ,  H04L12/863 ,  H04L12/861 ,  H04L12/935 ,  H04L12/801

    Abstract: An addressless merge command includes an identifier of an item of data, and a reference value, but no address. A first part of the item is stored in a first place. A second part is stored in a second place. To move the first part so that the first and second parts are merged, the command is sent across a bus to a device. The device translates the identifier into a first address ADR1, and uses ADR1 to read the first part. Stored in or with the first part is a second address ADR2 indicating where the second part is stored. The device extracts ADR2, and uses ADR1 and ADR2 to issue bus commands. Each bus command causes a piece of the first part to be moved. When the entire first part has been moved, the device returns the reference value to indicate that the merge command has been completed.

    Efficient Intercept Of Connection-Based Transport Layer Connections
    79.
    发明申请
    Efficient Intercept Of Connection-Based Transport Layer Connections 有权

    公开(公告)号：US20180212879A1

    公开(公告)日：2018-07-26

    申请号：US15924193

    申请日：2018-03-17

    Applicant: Netronome Systems, Inc.

    Inventor： Roelof Nico du Toit ,  Jacques Fourie ,  Peter Liudmilov Djalaliev

    IPC: H04L12/801 ,  H04L29/06

    CPC classification number: H04L47/10 ,  H04L29/06 ,  H04L63/0281 ,  H04L63/0464 ,  H04L63/0823 ,  H04L63/166 ,  H04L69/163

    Abstract: A TCP connection is established between a client and a server, such that packets communicated across the TCP connection pass through a proxy. Based at least in part on a result of monitoring packets flowing across the TCP connection, the proxy determines whether to split the TCP control loop into two TCP control loops so that packets can be inspected more thoroughly. If the TCP control loop is split, then a first TCP control loop manages flow between the client the proxy and a second TCP control loop manages flow between the proxy and the server. Due to the two control loops, packets can be held on the proxy long enough to be analyzed. In some circumstances, a decision is then made to stop inspecting. The two TCP control loops are merged into a single TCP control loop, and thereafter the proxy passes packets of the TCP connection through unmodified.

    Low cost multi-server array architecture
    80.
    发明授权
    Low cost multi-server array architecture 有权

    公开(公告)号：US10034070B1

    公开(公告)日：2018-07-24

    申请号：US14846797

    申请日：2015-09-06

    Applicant: Netronome Systems, Inc.

    Inventor： J. Niel Viljoen

    IPC: H04J14/00 ,  H04Q11/00

    Abstract: An array of columns and rows of host server devices is mounted in a row of racks. Each device has a host processor and an exact-match packet switching integrated circuit. Packets are switched within the system using exact-match flow tables that are provisioned by a central controller. Each device is coupled by a first cable to a device to its left, by a second cable to a device to its right, by a third cable to a device above, and by a fourth cable to a device below. In one example, substantially all cables that are one meter or less in length are non-optical cables, whereas substantially all cables that are seven meters or more in length are optical cables. Advantageously, each device of a majority of the devices has four and only four cable ports, and connects only to non-optical cables, and the connections involve no optical transceiver.

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