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公开(公告)号:US11381233B2
公开(公告)日:2022-07-05
申请号:US16028559
申请日:2018-07-06
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Philippe Bienvenu , Antonio Calandra
IPC: H03K17/082 , H03K5/24 , H03K3/037 , H02H3/20 , H02H3/00
Abstract: A protection circuit for a transistor switch coupled to a power supply rail operates to modulate a control voltage at a control terminal of the transistor switch. A first circuit detects an overload across the terminals of the switch with respect to a threshold to generate a signal which modulates the control voltage. A second circuit operates to adjust a value of the threshold in response to sensed variations in a supply voltage at the power supply rail.
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72.
公开(公告)号:US11367720B2
公开(公告)日:2022-06-21
申请号:US16518436
申请日:2019-07-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Pascal Fornara , Fabrice Marinet
IPC: H01L27/02 , H01L23/525
Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.
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公开(公告)号:US20220164664A1
公开(公告)日:2022-05-26
申请号:US17510273
申请日:2021-10-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Pierre Demaj , Laurent Folliot
Abstract: According to one aspect, the disclosure proposes a method for updating an artificial neural network including initial weights stored in a memory at least in an integer format, which method includes: a processing unit determining the error gradients at the output of the layers of the neural network, the processing unit retrieving the initial weights from memory, the processing unit updating the initial weights comprising, for each initial weight, a first calculation of a corrected weight, in the integer format of this initial weight, the processing unit replacing the value of the initial weights stored in the memory by the value of the corrected weights.
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公开(公告)号:US11336268B2
公开(公告)日:2022-05-17
申请号:US17128890
申请日:2020-12-21
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Bruno Gailhard
Abstract: Integrated circuit, comprising at least one ring oscillator including a succession of inverters looped back to form the ring, the at least one oscillator being intended to operate at a desired output frequency and configured so that the inverter transistors operate in or near their temperature inversion zone.
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公开(公告)号:US20220150680A1
公开(公告)日:2022-05-12
申请号:US17649146
申请日:2022-01-27
Applicant: STMicroelectronics (Rousset) SAS , STMICROELECTRONICS GMBH
Inventor: Thierry Meziache , Pierre Rizzo , Alexandre Charles , Juergen Boehler
Abstract: A device, including a main element and a set of at least two auxiliary elements, said main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to said master SWP interface of said NFC element through a controllably switchable SWP link and management means configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.
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公开(公告)号:US20220149894A1
公开(公告)日:2022-05-12
申请号:US17499371
申请日:2021-10-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Alexandre Tramoni
Abstract: An embodiment of the present description concerns a method wherein a time of beginning of a periodic step of activation of a near-field communication circuit of a first device, charged in near field by a second device, is adjusted according to a frequency of an electromagnetic field emitted by the second device.
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公开(公告)号:US11322503B2
公开(公告)日:2022-05-03
申请号:US17141498
申请日:2021-01-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Pascal Fornara , Fabrice Marinet
IPC: G11C17/16 , H01L27/112 , H01L23/58 , H01L23/528 , G11C17/18 , H01L23/525 , H01L23/522
Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
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公开(公告)号:US20220130904A1
公开(公告)日:2022-04-28
申请号:US17507624
申请日:2021-10-21
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor: Philippe BOIVIN
Abstract: The present description concerns a method of forming a track in a first layer, including a) forming a cavity in the first layer; b) totally filling the cavity with a first material; and c) partially removing the first material from the upper portion of the cavity, to form the track made of the first material.
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公开(公告)号:US20220129568A1
公开(公告)日:2022-04-28
申请号:US17484246
申请日:2021-09-24
Inventor: Olivier Van Nieuwenhuyze , Alexandre Charles
IPC: G06F21/60
Abstract: The present description discloses a secure element and a communication method, configured to implement at least one first application, and including a circuit configured to record routing data and a list and parameters of communication protocols compatible with the first application, verify the compatibility of a first communication protocol used by first messages intended for the first application with the protocols of the list, convert the first messages into second messages by using a second communication protocol in response to the first protocol not being compatible with at least one of the protocols of the list, and direct the second messages to the first application by using the routing data of the first application.
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公开(公告)号:US20220120589A1
公开(公告)日:2022-04-21
申请号:US17504021
申请日:2021-10-18
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Pascal FORNARA
Abstract: An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.
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