公开(公告)号：US11520721B2

公开(公告)日：2022-12-06

申请号：US16933752

申请日：2020-07-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Nirav Prashantkumar Trivedi ,  Sandip Atal ,  Rolf Nandlinger

IPC: G06F13/00 ,  G06F13/28 ,  H03M1/38 ,  H03M1/12

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

公开(公告)号：US20220334865A1

公开(公告)日：2022-10-20

申请号：US17657856

申请日：2022-04-04

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G06F9/455 ,  G06F11/07

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.

公开(公告)号：US20220318173A1

公开(公告)日：2022-10-06

申请号：US17806587

申请日：2022-06-13

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20220191059A1

公开(公告)日：2022-06-16

申请号：US17539936

申请日：2021-12-01

Applicant: STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred RENNIG ,  Rolf NANDLINGER

IPC: H04L12/40 ,  G06F13/42 ,  G06F13/40

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

公开(公告)号：US11321492B2

公开(公告)日：2022-05-03

申请号：US17107183

申请日：2020-11-30

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio ,  Lorenzo Re Fiorentin

IPC: G06F9/448 ,  G06F12/02 ,  G06F9/38 ,  G06F9/30 ,  G06F21/71 ,  G06F21/60 ,  H04L9/06 ,  G06F11/07 ,  G06F21/57 ,  G06F21/72 ,  G06F21/77 ,  H03K19/17728

Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.

公开(公告)号：US11068255B2

公开(公告)日：2021-07-20

申请号：US16829280

申请日：2020-03-25

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F9/44 ,  G06F21/57 ,  G06F9/445 ,  G06F1/24 ,  G06F9/4401 ,  G06F8/654 ,  G06F11/27 ,  G06F12/10

Abstract: A processing system includes a digital processing unit, one or more non-volatile memories configured to store a firmware to be executed by the digital processing unit, a diagnostic circuit configured to execute a self-test operation of the processing system in response to a diagnostic mode enable signal, and a reset circuit. The reset circuit is configured to perform a complex reset of the processing system by generating a first reset of the processing system in response to a given event and generating a second reset of the processing system once the self-test operation has been executed. The processing system is configured to set the diagnostic mode enable signal in response to the first reset, thereby activating execution of the self-test operation.

公开(公告)号：US11048525B2

公开(公告)日：2021-06-29

申请号：US16273704

申请日：2019-02-12

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Roberto Colombo ,  Om Ranjan

IPC: G06F13/36 ,  G06F9/445 ,  H04L9/06 ,  H04L9/32 ,  G06F11/10

Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.

公开(公告)号：US20210089329A1

公开(公告)日：2021-03-25

申请号：US17107183

申请日：2020-11-30

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Roberto COLOMBO ,  Nicolas BERNARD GROSSIER ,  Giovanni DISIRIO ,  Lorenzo RE FIORENTIN

IPC: G06F9/448 ,  G06F12/02 ,  G06F9/38 ,  G06F9/30 ,  G06F21/71 ,  G06F21/60

Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.

公开(公告)号：US10678726B2

公开(公告)日：2020-06-09

申请号：US16360229

申请日：2019-03-21

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GmbH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20190159369A1

公开(公告)日：2019-05-23

申请号：US16259442

申请日：2019-01-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Domenico Massimo Porto ,  Giovanni Luca Torrisi ,  Manuel Gaertner ,  Sergio Lecce

IPC: H05K7/20 ,  H01L23/34

Abstract: A thermal control process for an electronic power device including a multi junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.