Method and device for optimizing signal power on a wired communications network
    71.
    发明授权
    Method and device for optimizing signal power on a wired communications network 有权
    用于优化有线通信网络上的信号功率的方法和设备

    公开(公告)号:US08013467B2

    公开(公告)日:2011-09-06

    申请号:US11676309

    申请日:2007-02-19

    Applicant: Song-Lin Young

    Inventor: Song-Lin Young

    Abstract: A method and network device increases the power of the signal transmitted by the device on a wired communications network, such as a powerline communications (PLC) network, without exceeding the maximum allowable common-mode (CM) current specified by regulatory bodies. The device is first tested for regulatory body compliance on a standard network. The output voltage of the device is adjusted until the maximum allowable CM current is detected, and this voltage level and CM current are recorded and stored in non-volatile memory of the device. The device is then connected to the actual network and the output voltage set to the previously recorded value. At this voltage level, the CM current in the actual network is measured and recorded. The difference between the CM current measured with the device on the actual network and the maximum allowable CM current is calculated and used to calculate the amount the output power of the signal from the device can be increased without exceeding the maximum allowable CM current.

    Abstract translation: 一种方法和网络设备增加了诸如电力线通信(PLC)网络的有线通信网络上的设备发送的信号的功率,而不超过监管机构指定的最大允许共模(CM)电流。 该设备首先在标准网络上进行监管机构的兼容性测试。 调整设备的输出电压,直到检测到最大容许CM电流,并将该电压电平和CM电流记录并存储在器件的非易失性存储器中。 然后将设备连接到实际网络,并将输出电压设置为先前记录的值。 在该电压电平下,测量并记录实际网络中的CM电流。 计算与实际网络上的设备测量的CM电流和最大允许CM电流之间的差异,并用于计算可以增加来自器件的信号的输出功率而不超过最大允许CM电流的量。

    Integrated circuit capable of locating failure process layers
    73.
    发明授权
    Integrated circuit capable of locating failure process layers 失效
    能够定位故障过程层的集成电路

    公开(公告)号:US07464357B2

    公开(公告)日:2008-12-09

    申请号:US11341481

    申请日:2006-01-30

    CPC classification number: G01R31/318538 G01R31/31855

    Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.

    Abstract translation: 用于定位故障过程层的集成电路。 电路具有设置在其中的扫描链的基板,其具有连接以形成串联链的扫描单元。 每个连接根据由分配的路由层的设计规则提供的最小维度的布局约束形成。 由于分配的路由层中的连接被限制到最小限度,扫描链很容易受到与分配的路由层相关的进程变化的影响。 扫描链使得更容易定位导致扫描链的低产率的过程。

    Site coating material and the production method of the same
    74.
    发明申请
    Site coating material and the production method of the same 审中-公开
    现场涂料及其制作方法相同

    公开(公告)号:US20070196628A1

    公开(公告)日:2007-08-23

    申请号:US11418914

    申请日:2006-05-08

    CPC classification number: D21H19/62 D21H13/50 D21H19/82 Y10T428/24802

    Abstract: The production method of the coating material comprising the steps of applying and drying liquid polyurethane (PU) material onto a release paper in order to form three polyurethane (PU) layers, rolling the composite layer and separating the release paper to form the composite coating material for covering the outer shells of electronic devices. The polyurethane (PU) composite coating material thereby produced comprises at least a colored surface layer and a substrate layer. The surface of the composite coating material is colored and has a relief-like pattern, which can provide users with a better visual or touch effect.

    Abstract translation: 涂料的制备方法包括以下步骤:将液体聚氨酯(PU)材料施加并干燥到脱模纸上以形成三个聚氨酯(PU)层,滚动复合层并分离隔离纸以形成复合涂层材料 用于覆盖电子设备的外壳。 由此制备的聚氨酯(PU)复合涂层材料至少包括着色表面层和基底层。 复合涂层材料的表面是有色的并且具有浮雕状图案,其可以为使用者提供更好的视觉或触感效果。

    Child resistant actuator for piezoelectric lighter
    76.
    发明授权
    Child resistant actuator for piezoelectric lighter 失效
    用于压电打火机的防儿童执行器

    公开(公告)号:US06682341B2

    公开(公告)日:2004-01-27

    申请号:US10171204

    申请日:2002-06-15

    CPC classification number: F23Q2/164

    Abstract: A piezoelectric lighter with a child resistant ignition mechanism which prevents accidental ignition and ignition by unintended users and by minor children under the age of 5 years. The safety ignition mechanism is an activation device that requires two displacements in order to ignite the lighter. The displacements are achieved by applying a continuous and increasing force to the activating component in order to ignite the lighter. The first displacement unlocks the ignition device and the second displacement initiates simultaneously an electrical discharge and a fuel discharge, which results in a flame. Whenever a user discontinues the application of force to the activating component, the ignition mechanism returns to an inoperable, locked position. The effectiveness of this activating device in resisting the manipulations of children under the age of 5 years has been established by tests performed pursuant to the requirements of the United States Consumer Product Safety Commission.

    Abstract translation: 一种压电打火机,具有防儿童点火机构,可防止意外使用者和5岁以下未成年子女发生意外点燃和点燃。 安全点火机构是一种启动装置,需要两个位移才能点燃打火机。 通过对激活部件施加连续和增加的力以便点燃打火机来实现位移。 第一排量释放点火装置,第二排量同时启动放电和燃料排放,这导致火焰。 无论何时用户停止向激活部件施加力,点火机构返回到不能操作的锁定位置。 通过根据美国消费品安全委员会的要求进行试验,确立了这种激活装置在抵制5岁以下儿童操作方面的有效性。

    Method to combine high voltage device and salicide process
    77.
    发明授权
    Method to combine high voltage device and salicide process 有权
    高压装置与自动化处理相结合的方法

    公开(公告)号:US6110782A

    公开(公告)日:2000-08-29

    申请号:US195651

    申请日:1998-11-19

    CPC classification number: H01L27/11526 H01L21/823462 H01L27/11541

    Abstract: A method for integrating salicide and high voltage device processes in the fabrication of high and low voltage devices on a single wafer is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating a low voltage device area from a high voltage device area. A gate oxide layer is grown in the device areas. A polysilicon layer is deposited overlying the gate oxide layer and isolation areas. A first photomask is formed over a portion of the high voltage device area wherein the first photomask also completely covers the low voltage device area. The polysilicon layer is etched away where it is not covered by the photomask to form a high voltage device. Ions are implanted to form lightly doped source and drain regions within the semiconductor substrate adjacent to the high voltage device wherein the first photomask protects the polysilicon layer in the low voltage device area from the ions. The first photomask is removed. A second photomask is formed over a portion of the low voltage device area where a gate electrode is to be formed wherein the second photomask also completely covers the high voltage device area. The polysilicon layer not covered by the second photomask is etched away to form the gate electrode. The second photomask is removed. The low voltage and high voltage area devices are silicided and the fabrication of the integrated circuit device is completed.

    Abstract translation: 描述了在单个晶片上制造高电压和低压器件中的自对准硅化物和高电压器件工艺的集成方法。 在半导体衬底上形成隔离区域,该半导体衬底围绕低电压器件区域和高电压器件区域电隔离。 在器件区域中生长栅极氧化物层。 沉积覆盖栅极氧化物层和隔离区的多晶硅层。 第一光掩模形成在高电压器件区域的一部分上,其中第一光掩模也完全覆盖低电压器件区域。 多晶硅层被蚀刻掉,其未被光掩模覆盖以形成高压器件。 植入离子以在与高压器件相邻的半导体衬底内形成轻掺杂的源极和漏极区,其中第一光掩模保护低电压器件区域中的多晶硅层与离子。 第一个光掩模被删除。 第二光掩模形成在要形成栅电极的低电压器件区域的一部分上,其中第二光掩模也完全覆盖高电压器件区域。 蚀刻掉未被第二光掩模覆盖的多晶硅层以形成栅电极。 第二个光掩模被删除。 低电压和高电压区域的器件被硅化,并且完成了集成电路器件的制造。

    Divide-by-five divider
    78.
    发明授权
    Divide-by-five divider 失效
    除以五分频器

    公开(公告)号:US5140544A

    公开(公告)日:1992-08-18

    申请号:US772498

    申请日:1991-10-07

    CPC classification number: G06F7/535

    Abstract: A video display system includes a frame buffer includes five sets of one or more video random access memories. An address generator for generating address locations in the frame buffer generates ship select, row select and column select address signals. Because the frame buffer comprises five sets of video random access memories, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memeory capacity in the frame buffer.

    Abstract translation: 视频显示系统包括帧缓冲器,其包括五组一个或多个视频随机存取存储器。 用于在帧缓冲器中产生地址位置的地址发生器产生船选择,行选择和列选择地址信号。 因为帧缓冲器包括五组视频随机存取存储器,所以产生地址信号需要执行五分之一的操作。 因此,地址发生器包括唯一的除以5的电路,其中除法由一系列的加法和乘法执行。 与常规系统相比,本发明的视频系统在帧缓冲器中更有效地使用存储容量。

    CASTOR WITH SEPARATE BRAKE DEVICE AND BRAKE RELEASE DEVICE
    79.
    发明申请
    CASTOR WITH SEPARATE BRAKE DEVICE AND BRAKE RELEASE DEVICE 有权
    独立制动装置和制动器释放装置

    公开(公告)号:US20150096845A1

    公开(公告)日:2015-04-09

    申请号:US14045817

    申请日:2013-10-04

    Applicant: QING-SONG LIN

    Inventor: QING-SONG LIN

    Abstract: A castor with separate brake device and brake release device is provided with a shell, a brake piece, a brake unit and a brake-release unit. The brake unit and the brake-release unit are two separate members, while they are interactively linked by a push portion and the notch portion, so as to ensure the accuracy of the brake operation. Whenever the castor is in a brake-activated status or brake-deactivated status, the brake pedal and the brake-release pedal pivot in opposite direction to present different angles, which makes it easier for the user to see the status of the castor (in brake position or non-brake position), and prevents confusion or accidental operation.

    Abstract translation: 具有单独的制动装置和制动器释放装置的脚轮设置有壳体,制动片,制动单元和制动释放单元。 制动单元和制动器释放单元是两个单独的构件,而它们通过推动部分和切口部分交互地连接,以确保制动操作的精度。 每当脚轮处于制动器启动状态或制动器停用状态时,制动踏板和制动器释放踏板以相反方向枢转以呈现不同的角度,这使得用户更容易看到脚轮的状态(在 制动位置或非制动位置),并防止混乱或意外操作。

    Sequence control circuit for power source
    80.
    发明授权
    Sequence control circuit for power source 有权
    电源顺序控制电路

    公开(公告)号:US08810064B2

    公开(公告)日:2014-08-19

    申请号:US13181523

    申请日:2011-07-13

    Abstract: A sequence control circuit for power sources includes two switched circuits and a sequence control unit. Each of the switched circuits has a control node and is coupled between a power source and a load. The sequence control unit includes two output terminals coupled to the control nodes. The output terminals generate control signals to control the sequence of the circuits being turned on.

    Abstract translation: 用于电源的序列控制电路包括两个开关电路和一个序列控制单元。 每个开关电路具有控制节点并耦合在电源和负载之间。 序列控制单元包括耦合到控制节点的两个输出端。 输出端产生控制信号以控制电路接通的顺序。

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