公开(公告)号：US09000514B2

公开(公告)日：2015-04-07

申请号：US13560247

申请日：2012-07-27

申请人： Yeeheng Lee ,  Sung-Shan Tai ,  Hong Chang ,  John Chen

发明人： Yeeheng Lee ,  Sung-Shan Tai ,  Hong Chang ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/66719 ,  H01L29/66734

摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.

摘要翻译： 公开了半导体器件制造方法和器件。 可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。 或者，氧化物 - 氧化物 - 氧化物（ONO）结构可以形成在沟槽的侧壁和底部，并且可以在不被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

公开(公告)号：US08334566B2

公开(公告)日：2012-12-18

申请号：US12829349

申请日：2010-07-01

申请人： Sung-Shan Tai

发明人： Sung-Shan Tai

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention provides a semiconductor power device including a substrate, an epitaxial layer disposed on the substrate and having at least a first trench and a second trench, a gate structure disposed in the first trench, and a termination structure disposed in the second trench. The gate structure includes a gate electrode, a gate dielectric layer disposed on an upper sidewall of the first trench and between the gate electrode and the epitaxial laver, and a shield electrode disposed under the gate electrode. The termination structure includes a termination electrode and a dielectric layer disposed between the termination electrode and a sidewall of the second trench. The termination electrode and the shield electrode are connected to each other. In addition, a body region is disposed in the epitaxial layer, and the second trench is only surrounded by the body region.

摘要翻译： 本发明提供了一种半导体功率器件，其包括衬底，设置在衬底上的外延层，并且具有至少第一沟槽和第二沟槽，设置在第一沟槽中的栅极结构以及设置在第二沟槽中的端接结构。 栅极结构包括栅电极，设置在第一沟槽的上侧壁上以及栅电极和外延栅之间的栅电介质层，以及设置在栅极下方的屏蔽电极。 端接结构包括终端电极和布置在端接电极和第二沟槽的侧壁之间的电介质层。 终端电极和屏蔽电极彼此连接。 此外，体区域设置在外延层中，并且第二沟槽仅被身体区域包围。

公开(公告)号：US20120292693A1

公开(公告)日：2012-11-22

申请号：US13560247

申请日：2012-07-27

申请人： Yeeheng LEE ,  Sung-Shan TAI ,  Hong CHANG ,  John CHEN

发明人： Yeeheng LEE ,  Sung-Shan TAI ,  Hong CHANG ,  John CHEN

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/66719 ,  H01L29/66734

摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.

摘要翻译： 公开了半导体器件制造方法和器件。 可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。 或者，可以在沟槽的侧壁和底部形成氧化物 - 氧化物（ONO）结构，并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

公开(公告)号：US20120083084A1

公开(公告)日：2012-04-05

申请号：US13199795

申请日：2011-09-08

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/1082

摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

摘要翻译： 沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。 围绕沟槽栅极的源极区域包括低势垒高度的金属，用作肖特基源，并且可以包括PtSi，ErSi层，并且可以是具有低势垒高度的金属硅化物层。 顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。 源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。

公开(公告)号：US20120028427A1

公开(公告)日：2012-02-02

申请号：US13200882

申请日：2011-10-04

申请人： Sung-Shan Tai ,  YongZhong Hu

发明人： Sung-Shan Tai ,  YongZhong Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4958 ,  H01L29/66727 ,  H01L29/66734

摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

摘要翻译： 本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。 沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。 沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。 在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

公开(公告)号：US08105905B2

公开(公告)日：2012-01-31

申请号：US12927177

申请日：2010-11-08

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66734

摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.

摘要翻译： 一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源区域短接。

公开(公告)号：US08008151B2

公开(公告)日：2011-08-30

申请号：US11983769

申请日：2007-11-09

申请人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

发明人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

摘要翻译： 一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量 延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

公开(公告)号：US20110198588A1

公开(公告)日：2011-08-18

申请号：US13066583

申请日：2011-04-18

申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

公开(公告)号：US20110124167A1

公开(公告)日：2011-05-26

申请号：US12927177

申请日：2010-11-08

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66734

摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.

摘要翻译： 一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源极区域短接触。

公开(公告)号：US20110068386A1

公开(公告)日：2011-03-24

申请号：US12565611

申请日：2009-09-23

申请人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

发明人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 可以将沟槽掩模施加到半导体衬底，其被蚀刻以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上形成第二导电材料。 绝缘体层分离第一和第二导电材料。 第一绝缘体层沉积在沟槽的顶部。 主体层形成在基板的顶部。 源体形成在体层中。 第二绝缘体层被施加在沟槽和源的顶部上。 接触掩模施加在第二绝缘体层的顶部。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层的顶部上。